Fully synchronous: All signals are registered on the
positive edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full
Page
3.3V ± 0.3V Power Supply
144 Pin SO-DIMM JEDEC
• D1: 27.94 (1.10”)
WED3DG644V-D1
DESCRIPTION
The WED3DG644V is a 4Mx64 synchronous DRAM
module which consists of four 4Mx16 SDRAM components
in TSOP II package, and one 2Kb EEPROM in an 8
pin TSOP package for Serial Presence Detect which
are mounted on a 144 pin SO-DIMM multilayer FR4
Substrate.
* This product is subject to change without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
Pin Front Pin Back Pin Front Pin Back
1
V
SS
2
V
SS
51 DQ14 52 DQ46
3
DQ0
4 DQ32 53 DQ15 54 DQ47
5
DQ1
6 DQ33 55
V
SS
56 V
SSv
7
DQ2
8 DQ34 57
NC
58
NC
9
DQ3 10 DQ35 59
NC
60
NC
12
V
CC
11
V
CC
13 DQ4 14 DQ36
VOLTAGE KEY
15 DQ5 16 DQ37
17 DQ6 18 DQ38 61 CLK0 62 CKE0
19 DQ7 20 DQ39 63
V
CC
64
V
CC
21
V
SS
22
V
SS
65 RAS# 66 CAS#
23 DQM0 24 DQM4 67 WE# 68 *CKE1
25 DQM1 26 DQM5 69 CS0# 70 *A12
27
V
CC
28
V
CC
71 *CS1# 72 *A13
29
A0
30
A3
73 DNU 74 *CK1
76
V
SS
31
A1
32
A4
75
V
SS
33
A2
34
A5
77
NC
78
NC
35
V
SS
36
V
SS
79
NC
80
NC
37 DQ8 38 DQ40 81
V
CC
82
V
CC
39 DQ9 40 DQ41 83 DQ16 84 DQ48
41 DQ10 42 DQ42 85 DQ17 86 DQ49
43 DQ11 44 DQ43 87 DQ18 88 DQ50
45
V
CC
46
V
CC
89 DQ19 90 DQ51
47 DQ12 48 DQ44 91
V
SS
92
V
SS
49 DQ13 50 DQ45 93 DQ20 94 DQ52
Pin
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
Back
DQ21
DQ22
DQ23
V
CC
A6
A8
V
SS
A9
A10/AP
V
CC
DQM2
DQM3
V
SS
DQ24
DQ25
DQ26
DQ27
V
CC
DQ28
DQ29
DQ30
DQ31
V
SS
**SDA
V
CC
Pin Back
96 DQ53
98 DQ54
100 DQ55
102 V
CC
104
A7
106 BA0
108 V
SS
110 BA1
112 A11
114 V
CC
116 DQM6
118 DQM7
120 VSS
122 DQ56
124 DQ57
126 DQ58
128 DQ59
130 V
CC
132 DQ60
134 DQ61
136 DQ62
138 DQ63
140 V
SS
142 **SCL
144 V
CC
A0 – A11
BA0-1
DQ0-63
CLK0
CKE0
CS0#
RAS#
CAS#
WE#
DQM0-7
V
CC
V
SS
*V
REF
SDA
SCL
DNU
NC
PIN NAMES
Address input (Multiplexed)
Select Bank
Data Input/Output
Clock input
Clock Enable input
Chip select Input
Row Address Strobe
Column Address Strobe
Write Enable
DQM
Power Supply (3.3V)
Ground
Power supply for reference
Serial data I/O
Serial clock
Do not use
No Connect
* These pins are not used in this module.
** These pins should be NC in the system
which does not support SPD.
September 2007
Rev. 5
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
WED3DG644V-D1
CS0#
DQM0
DQM4
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM2
LDQM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM6
CS#
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A0-A11
BA0
RAS#
CAS#
WE#
CKE0
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SERIAL PD
SCL
WP
47Ω
A0
A1
A2
SDA
V
CC
V
CC
10Ω
TWO 0.1 uF CAPACITORS
To all SDRAMS
PER EACH SDRAM
CLK0
10Ω
SDRAM
SDRAM
SDRAM
SDRAM
Notes: D1 option does not have series resistors.
September 2007
Rev. 5
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Current
Symbol
V
IN
, V
OUT
V
CC
, V
CCQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
WED3DG644V-D1
Units
V
V
°C
W
mA
-55 ~ +150
4
50
Note: Permanent device damage may occur if “ABSOLUTE MAXIMUM RATINGS” are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: V
SS
= 0V, T
A
= 0°C to +70°C
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
Symbol
V
CC
V
IH
V
IL
V
OH
V
OL
I
LI
Min
3.0
2.0
-0.3
2.4
—
-10
Typ
3.3
3.0
—
—
—
—
Max
3.6
V
CCQ+0.3
0.8
—
0.4
10
Unit
V
V
V
V
V
μA
1
2
I
OH
= -2mA
I
OL
= -2mA
3
Note
Note: 1. V
IH
(max)= 5.6V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min)= -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
CCQ
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-State outputs.
CAPACITANCE
T
A
= 25°C, f = 1MHz, V
CC
= 3.3V, V
REF
= 1.4V
±
200mV
Parameter
Input Capacitance (A0-A12)
Input Capacitance (RAS#,CAS#,WE#)
Input Capacitance (CKE0)
Input Capacitance (CLK0)
Input Capacitance (CS0#)
Input Capacitance (DQM0-DQM7)
Input Capacitance (BA0-BA1)
Data Input/Output Capacitance (DQ0-DQ63)
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
IN6
C
IN7
C
OUT
Max
25
25
25
19
25
8
25
10
Unit
pF
pF
pF
pF
pF
pF
pF
pF
September 2007
Rev. 5
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
OPERATING CURRENT CHARACTERISTICS
(V
CC
= 3.3V, T
A
= 0°C to +70°C)
Parameter
Operating Current
(One bank active)
Precharge Standby Current
in Power Down Mode
Symbol
Conditions
Burst Length = 1
t
RC
t
RC
(min)
I
OL
= 0mA
CKE V
IL
(max), t
CC
= 10ns
CKE & CLK V
IL
(max), t
CC
=
∞
CKE V
IH
(min), CS V
IH
(min), tcc =10ns
Input signals are charged one time during 20
CKE V
IH
(min), CLK V
IL
(max), t
CC
=
∞
Input signals are stable
CKE V
IL
(max), t
CC
= 10ns
CKE & CLK V
IL
(max), t
CC
=
∞
CKE V
IH
(min), CS V
IH
(min), tcc = 10ns
Input signals are changed one time during 20ns
CKE V
IH
(min), CLK V
IL
(max), tcc =
∞
Input signals are stable
Io = mA
Page burst
4 Banks activated
t
CCD
= 2CLK
t
RC
t
RC
(min)
CKE 0.2V
WED3DG644V-D1
Version
133/100
300
Units
Note
I
CC1
I
CC2P
I
CC2PS
I
CC2N
mA
1
4
4
48
24
8
8
80
40
mA
Precharge Standby Current
in Non-Power Down Mode
Active Standby Current in
Power-Down Mode
I
CC2NS
I
CC3P
I
CC3PS
I
CC3N
mA
mA
mA
mA
Active Standby Current in
Non-Power Down Mode
I
CC3NS
Operating Current (Burst mode)
Refresh Current
Self Refresh Current
Notes:
1.
Measured with outputs open.
2.
Refresh period is 64ms.
I
CC4
I
CC5
I
CC6
460
360
4
mA
mA
mA
1
2
September 2007
Rev. 5
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
AC OPERATING TEST CONDITIONS
V
CC
= 3.3V ± 0.3V, 0
≤
T
A
≤
70°C
Parameter
AC input levels (V
IH
/V
IL
)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Value
2.4/0.4
1.4
t
R
/t
F
= 1/1
1.4
WED3DG644V-D1
Unit
V
V
ns
V
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
RAS# to CAS# delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
Symbol
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
t
RC
(min)
t
RDL
(min)
t
DAL
(min)
t
CDL
(min)
t
BDL
(min)
t
CCD
(min)
CAS latency=3
CAS latency=2
Version
7.5, 10
15
20
20
45
100
65
2
2 CLK + t
RP
1
1
1
2
1
Unit
ns
ns
ns
ns
us
ns
CLK
—
CLK
CLK
CLK
ea
2
2
3
4
1
2
Note
1
1
1
1
Notes :
1.
The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer.
2.
Minimum delay is required to complete write.
3.
All parts allow every cycle column address change.
4.
In case of row precharge interrupt, auto precharge and read burst stop.
September 2007
Rev. 5
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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