W29N08GVXXAF
2 CHIP STACKED 8G-BIT
W29N08GVXXAF
8G-BIT 3.3V
NAND FLASH MEMORY
1
Release Date: September 27
th
, 2018
Revision B
W29N08GVXXAF
Table of Contents
1.
2.
3.
GENERAL DESCRIPTION ............................................................................................................ 7
FEATURES .................................................................................................................................... 7
PACKAGE TYPES AND PIN CONFIGURATIONS ....................................................................... 8
3.1
Pin Assignment 48-pin TSOP1 ............................................................................................. 8
3.2
Pin Assignment 63-ball VFBGA ............................................................................................ 9
3.3
Pin Descriptions .................................................................................................................. 10
PIN DESCRITPIONS ................................................................................................................... 11
4.1
Chip Enable (#CE) .............................................................................................................. 11
4.2
Write Enable (#WE) ............................................................................................................ 11
4.3
Read Enable (#RE) ............................................................................................................. 11
4.4
Address Latch Enable (ALE) .............................................................................................. 11
4.5
Command Latch Enable (CLE) ........................................................................................... 11
4.6
Write Protect (#WP) ............................................................................................................ 11
4.7
Ready/Busy (RY/#BY) ........................................................................................................ 11
4.8
Input and Output (I/Ox) ....................................................................................................... 11
SINGLE DIE BLOCK DIAGRAM .................................................................................................. 12
MEMORY ARRAY ORGANIZATION ........................................................................................... 13
6.1
Array Organization ............................................................................................................ 13
MODE SELECTION TABLE ........................................................................................................ 14
COMMAND TABLE ...................................................................................................................... 15
DEVICE OPERATIONS ............................................................................................................... 17
9.1
READ Operation ................................................................................................................. 17
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.1.7
9.1.8
9.1.9
PAGE READ (00h-30h) ........................................................................................................ 17
CACHE READ OPERATIONS .............................................................................................. 17
TWO PLANE READ (00h-00h-30h) ...................................................................................... 21
RANDOM DATA OUTPUT (05h-E0h) ................................................................................... 23
READ ID (90h) ...................................................................................................................... 25
READ PARAMETER PAGE (ECh) ....................................................................................... 26
READ STATUS (70h) ........................................................................................................... 28
READ STATUS ENHANCED (78h) ...................................................................................... 30
READ UNIQUE ID (EDh) ...................................................................................................... 31
PAGE PROGRAM (80h-10h) ................................................................................................ 32
SERIAL DATA INPUT (80h) ................................................................................................. 32
RANDOM DATA INPUT (85h) .............................................................................................. 33
CACHE PROGRAM (80h-15h) ............................................................................................. 33
TWO PLANE PAGE PROGRAM .......................................................................................... 35
READ for COPY BACK (00h-35h) ........................................................................................ 38
PROGRAM for COPY BACK (85h-10h) ................................................................................ 38
TWO PLANE READ for COPY BACK ................................................................................... 39
TWO PLANE PROGRAM for COPY BACK .......................................................................... 39
4.
5.
6.
7.
8.
9.
9.2
PROGRAM Operation ........................................................................................................ 32
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.3
COPY BACK Operation ...................................................................................................... 38
9.3.1
9.3.2
9.3.3
9.3.4
9.4
BLOCK ERASE Operation .................................................................................................. 43
Release Date: September 27
th
, 2018
2
Revision B
W29N08GVXXAF
9.4.1
BLOCK ERASE (60h-D0h) ................................................................................................... 43
9.4.2 TWO PLANE BLOCK ERASE.................................................................................................. 44
9.5
9.6
RESET Operation ............................................................................................................... 45
9.5.1
9.6.1
9.6.2
RESET (FFh) ........................................................................................................................ 45
GET FEATURES (EEh) ........................................................................................................ 49
SET FEATURES (EFh) ......................................................................................................... 50
FEATURE OPERATION ..................................................................................................... 46
9.7
9.8
9.9
10.
ONE TIME PROGRAMMABLE (OTP) area ....................................................................... 51
WRITE PROTECT .............................................................................................................. 52
BLOCK LOCK ..................................................................................................................... 54
ELECTRICAL CHARACTERISTICS ............................................................................................ 55
10.1 Absolute Maximum Ratings (3.3V) ..................................................................................... 55
10.2 Operating Ranges (3.3V) .................................................................................................... 55
10.3 Device Power-up Timing..................................................................................................... 56
10.4 DC Electrical Characteristics (3.3V) ................................................................................... 57
10.5 AC Measurement Conditions (3.3V) ................................................................................... 58
10.6 AC Timing Characteristics for Command, Address and Data Input (3.3V) ........................ 59
10.7 AC Timing Characteristics for Operation (3.3V) ................................................................. 60
10.8 Program and Erase Characteristics .................................................................................... 61
TIMING DIAGRAMS .................................................................................................................... 62
INVALID BLOCK MANAGEMENT ............................................................................................... 72
12.1 Invalid Blocks ...................................................................................................................... 72
12.2 Initial Invalid Blocks ............................................................................................................ 72
12.3 Error in Operation ............................................................................................................... 73
12.4 Addressing in Program Operation ...................................................................................... 74
PACKAGE DIMENSIONS ............................................................................................................ 75
13.1 TSOP 48-pin 12x20 ............................................................................................................ 75
13.2 Fine-Pitch Ball Grid Array 63-ball ....................................................................................... 76
ORDERING INFORMATION ....................................................................................................... 77
VALID PART NUMBERS ............................................................................................................. 78
REVISION HISTORY ................................................................................................................... 79
11.
12.
13.
14.
15.
16.
3
Release Date: September 27
th
, 2018
Revision B
W29N08GVXXAF
List of Tables
Table 3-1 Pin Descriptions ..........................................................................................................................10
Table 6-1 Addressing ..................................................................................................................................13
Table 7-1 Mode Selection ...........................................................................................................................14
Table 8-1 Command Table ..........................................................................................................................16
Table 9-1 Device ID and Configuration Codes for Address 00h .................................................................26
Table 9-2 ONFI Identifying Codes for Address 20h ....................................................................................26
Table 9-3 Parameter Page Output Value ....................................................................................................28
Table 9-4 Status Register Bit Definition ......................................................................................................29
Table 9-5 Features ......................................................................................................................................46
Table 9-6 Feature Address 80h ...................................................................................................................47
Table 9-7 Feature Address 81h ...................................................................................................................48
Table 10-1 Absolute Maximum Ratings ......................................................................................................55
Table 10-2 Operating Ranges .....................................................................................................................55
Table 10-3 DC Electrical Characteristics ....................................................................................................57
Table 10-4 AC Measurement Conditions ....................................................................................................58
Table 10-5 AC Timing Characteristics for Command, Address and Data Input .........................................59
Table 10-6 AC Timing Characteristics for Operation ..................................................................................60
Table 10-7 Program and Erase Characteristics ..........................................................................................61
Table 12-1 Valid Block Number...................................................................................................................72
Table 12-2 Block Failure .............................................................................................................................73
Table 15-1 Part Numbers for Industrial Grade Temperature ......................................................................78
Table 15-2 Part Numbers for Industrial Plus Grade Temperature ..............................................................78
Table 16-1 History Table .............................................................................................................................79
4
Release Date: September 27
th
, 2018
Revision B
W29N08GVXXAF
List of Figures
Figure 3-1 Pin Assignment 48-pin TSOP1 (Package code S) ...................................................................... 8
Figure 3-3 Pin Assignment 63-ball VFBGA (Package code B) ..................................................................... 9
Figure 6-1 Single Die Array Organization ...................................................................................................13
Figure 9-1 Page Read Operations ..............................................................................................................17
Figure 9-2 Sequential Cache Read Operations ..........................................................................................19
Figure 9-3 Random Cache Read Operation ...............................................................................................20
Figure 9-4 Last Address Cache Read Operation ........................................................................................21
Figure 9-5 Two Plane Read Page (00h-00h-30h) Operation ......................................................................22
Figure 9-6 Random Data Output .................................................................................................................23
Figure 9-7 Two Plane Random Data Read (06h-E0h) Operation ...............................................................24
Figure 9-8 Read ID ......................................................................................................................................25
Figure 9-9 Read Parameter Page ...............................................................................................................26
Figure 9-10 Read Status Operation ............................................................................................................29
Figure 9-11 Read Status Enhanced (78h) Operation .................................................................................30
Figure 9-12 Read Unique ID .......................................................................................................................31
Figure 9-13 Page Program ..........................................................................................................................32
Figure 9-14 Random Data Input ..................................................................................................................33
Figure 9-15 Cache Program Start ...............................................................................................................34
Figure 9-16 Cache Program End ................................................................................................................34
Figure 9-17 Two Plane Page Program ........................................................................................................36
Figure 9-18 Two Plane Cache Program ......................................................................................................37
Figure 9-19 Program for Copy Back Operation ...........................................................................................40
Figure 9-20 Copy Back Operation with Random Data Input .......................................................................40
Figure 9-21 Two Plane Copy Back..............................................................................................................41
Figure 9-22 Two Plane Copy Back with Random Data Input ......................................................................41
Figure 9-23 Two Plane Program for Copy Back .........................................................................................42
Figure 9-24 Block Erase Operation .............................................................................................................43
Figure 9-25 Two Plane Block Erase Operation ...........................................................................................44
Figure 9-26 Reset Operation .......................................................................................................................45
Figure 9-27 Get Feature Operation .............................................................................................................49
Figure 9-28 Set Feature Operation .............................................................................................................50
Figure 9-29 Erase Enable ...........................................................................................................................52
Figure 9-30 Erase Disable ...........................................................................................................................52
Figure 9-31 Program Enable .......................................................................................................................52
Figure 9-32 Program Disable ......................................................................................................................53
Figure 9-33 Program for Copy Back Enable ...............................................................................................53
Figure 9-34 Program for Copy Back Disable ..............................................................................................53
Figure 10-1 Power ON/OFF sequence .......................................................................................................56
Figure 11-1 Command Latch Cycle.............................................................................................................62
Figure 11-2 Address Latch Cycle ................................................................................................................62
Figure 11-3 Data Latch Cycle ......................................................................................................................63
Figure 11-4 Serial Access Cycle after Read ...............................................................................................63
Figure 11-5 Serial Access Cycle after Read (EDO) ....................................................................................64
Figure 11-6 Read Status Operation ............................................................................................................64
Release Date: September 27
th
, 2018
Revision B
5
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