TDA9206
I
2
C BUS CONTROLLED 130MHz RGB PREAMPLIFIER
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130MHz TYPICAL BANDWIDTH AT 2V
PP
OUTPUT WITH 12pF CAPACITIVE LOAD
2.8ns TYPICAL RISE/FALL TIME AT 2V
PP
OUTPUT WITH 12pF CAPACITIVE LOAD
POWERFULL OUTPUT DRIVE CAPABILITY
BRT, CONT, DRIVE, OUTPUT DC LEVEL,
OSD CONTRAST, BACK-PORCH CLAMPING
PULSE WIDTH ARE I
2
C BUS CONTROLLED
INTERNAL
BACK-PORCH
CLAMPING
PULSE GENERATOR
OSD WHITE BALANCE TRACKING
INTERNAL OSD SWITCHES
BLANKING AND FAST-BLANKING INPUTS
VERY LARGE DRIVE ADJUSTMENT RANGE
(48dB)
SEMI-TRANSPARENT BACKGROUND ON
OSD PICTURE
DIP24
(Plastic Package)
ORDER CODE :
TDA9206
PIN CONNECTIONS
IN1
OSD1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
HSYNC
PV
CC1
OUT1
PGND1
PV
CC2
OUT2
PGND2
PV
CC3
OUT3
PGND3
BLK
FBLK
9206-01.EPS
DESCRIPTION
The TDA9206 is a digitaly controlled wideband
video preamplifier intended for use in high resolu-
tion color monitor. All controls and adjustments are
digitaly performed thanks to I
2
C serial bus. Con-
trast, brightness and DC output level of RGB sig-
nals are common to the 3 channels and drive
adjustment is separate for each channel. Three I
2
C
gain controlled OSD inputs can be switched with
RGB signals using fast blanking command. Clamp-
ing of RGB signals is performed thanks to a flexible
integrated system. The white balance adjustment
is effective on brightness, video and OSD signals.
The TDA9206works for application usingAC or DC
coupled CRT driver.
Because of its features and due to component
saving the TDA9206 leads to a very performantand
cost effective application.
September 1996
AV
DD
IN2
OSD2
AGND
IN3
OSD3
LV
DD
LGND
SDA
SCL
1/12
TDA9206
PIN DESCRIPTION
Name
IN1
OSD1
AV
DD
IN2
OSD2
AGND
IN3
OSD3
LV
DD
LGND
SDA
SCL
Pin
1
2
3
4
5
6
7
8
9
10
11
12
Type
I
I
I
I
I
I/O
I
I
I
I/O
I/O
I
st
st
Function
1 Channel Main Picture Input
1 Channel OSD Input
12V Analog V
DD
2
2
nd
nd
Name
FBLK
BLK
PGND3
OUT3
PV
CC3
PGND2
OUT2
PV
CC2
PGND1
OUT1
PV
CC1
HSYNC
Pin
13
14
15
16
17
18
19
20
21
22
23
24
Type
I
I
I/O
O
I
I/O
O
I
I/O
O
I
I
Function
Fast Blanking Input
Blanking Input
3
rd
Channel Power Ground
3 Channel Output
3 Channel Power V
CC
2
nd
Channel Power Ground
2
2
nd
nd
st
st
st
rd
rd
Channel Main Picture Input
Channel OSD Input
Analog Ground
3 Channel Main Picture Input
3 Channel OSD Input
12V Logic V
DD
Logic Ground
Serial Data Line
Serial Clock Line
rd
rd
Channel Output
Channel Power V
CC
1 Channel Power Ground
1 Channel Output
1 Channel Power V
CC
Horizontal Synch Input
9206-01.TBL
9206-02.EPS
BLOCK DIAGRAM
BLK
14
FBLK
13
P V
CC1
23
CLAMP
V
REF
3
1
BRIGHTNESS
DRIVE
BP C P
CO NTRAST
AV
DD
IN1
AGND
OUTPUT
STAGE
22
OUT1
21
PGND1
6
8 bits
IN2
4
20
PV
CC2
19
OUT2
18
PGND2
BLUE CHANNEL
IN3
LV
DD
7
9
GREEN C HANNEL
16
OUT3
17
PV
CC3
LGND
10
BP CP
15
PGND3
LATCHES
I
2
C
D/A
BUS
DECODER
OSD
CONT
I
2
C
V
REF
O UTPUT
DC LEVEL
ADJ US T
TDA9206
24
11
12
2
5
8
HS YNC
SDA
SCL
OSD1
OSD2
OSD3
2/12
TDA9206
FUNCTIONAL DESCRIPTION
Input Stage
The R, G and B signals must be fed to the three
inputs through coupling capacitors (100nF).
The maximum input peak-to-peak video amplitude
is 1V.
The input stage includes a clamping function. This
clamp is using the input serial capacitor as ”mem-
ory capacitor” and is gated by an internally gener-
ated ”Back-Porch-Clamping-Pulse (BPCP)”.
The synchronization edge of the BPCP is selected
according bit 0 of register R8.
When B0R8 is set to 1, the BPCP is synchronized
on the leading edge of the blanking pulse BLK
inputs on Pin 14 (see Figure 1).
Figure 1
BLK
HSYNC
BPCP
9206-04.EPS
9206-05.EPS
This DC-Offset is present only outside the blanking
pulse (see Figure 3).
The DC output level during the blanking pulse, is
forced to ”INFRA-BLACK” level (V
DC
).
Drive Adjustment
(3 x 8 bits)
In order to adjust the white balance , the TDA9206
offers the possibility to adjust separately the overall
gain of each complete video channel.
The gain of each channel is controlled by I
2
C (8bits
each).
The very large drive adjustment range (48dB) allows
different standard or custom color temperature.
It can also be used to adjust the output voltages at
the optimum amplitude to drive the C.R.T drivers,
keeping the whole contrast control for end-user only.
The drive adjustment is located after the CON-
TRAST, BRIGHTNESS and OSD switch blocks, so
that the white balance will remains correct when
BRT is adjusted, and will also be correct on OSD
portion of the signal.
OSD Inputs
The TDA9206 includes all the circuitry necessary
to mix OSD signals into the RGB main-picture. Four
pins are dedicated to this function as follow.
Three TTL RGB On Screen Display inputs
(Pin 2, 5 and 8). These three inputs are connected
to the three outputs of the corresponding ON-
SCREEN-DISPLAY processor (ex : STV942x).
One Fast Blanking Input (FBLK, Pin 13) which is
also connected to the FBLK output of the same
ON-SCREEN-DISPLAY processor.
When a high level is present on FBLK, the IC will
acts as follow :
- The three main picture RGB input signals are
internally switched to the internal input clamp
reference voltage.
- The three output signals are set to voltages
corresponding to the state (0 or 1) on the three
OSD inputs (see Figure 3).
Example :
If FBLK = 1 and OSD1, OSD2, OSD3) = 1, 0, 1
respectively.
Then OUT1, OUT2, OUT3 will be equal to V
OSD
,
V
BRT
, V
OSD
,
where : V
BRT
= V
BLACK
+ BRT
V
OSD
= V
BRT
+ OSD
BRT is the brightness DC level I
2
C adjustable.
OSD is the On-Screen Display signal value I
2
C
adjustable from 0V to 4.68V
PP
by step of 0.312V.
Semi-transparent function is controlled thanks to
Bit 6 of R8 register (see Table 1).
When semi-transparent mode is activated, video
signal is divided by 2 (CONT).
3/12
Internal pulse width is controlled by I
2
C
When B0R8 is clear to 0, the BPCP is synchronized
on the second edge of the horizontal pulse HSYNC
inputs on Pin 24. An automatic function allows to
use positive or negative horizontal pulse on Pin 24
(see Figure 2).
Figure 2
HSYNC
BPCP
Internal pulse width is controlled by I
2
C
In both case BPCP width is adjustable by I
2
C, B1
and B2 of register R8 (see R8 Table P8).
Contrast Adjustment
(8 bits)
The contrast adjustment is made by controlling
simultaneously the gain of three internal variable
gain amplifiers through the I
2
C bus interface.
The contrast adjustment allows to cover a typical
range of 48dB.
Brightness Adjustment
(8 bits)
As for the contrast adjustment, the brightness is
controlled by I
2
C.
The brightness function consists to add the same
DC offset to the three R, G, B signals after contrast
amplification.
TDA9206
FUNCTIONAL DESCRIPTION
(continued)
Table 1
FBLK OSD1 OSD2 OSD3 B6R8
0
1
0
1
1
1
1
x
x
x
0
x
x
1
x
x
x
x
1
x
0
x
x
x
x
x
0
1
0
0
1
1
1
1
1
Output
Signal (OUTn)
Video
OSD (1)
Video
OSD
OSD
OSD
Semi-trans-
parent (2)
- The output CLAMP : The IC also incorporates
three internal output clamp (sample and hold
system) which allow to DC shift the three output
signals. The DC output voltage is adjustable
through I
2
C with 4 bits. Practicaly, the DC output
level allow to adjust the BLK level
(V
DC
= 400mV under V
BLACK
) from 0.9V to 2.9V
with 12 x 165mV.
The overall waveforms of the output signal ac-
cording to the different adjustment are shown in
Figures 3 and 4.
Serial Interface
The 2-wires serial interface is an I
2
C interface.
The slave address of the TDA9206 is DC (in hexa-
decimal).
A6
1
A5
1
A4
0
A3
1
A2
1
A1
1
A0
0
W
0
Notes :
1. All OSD colors are displayed.
2. One OSD color is displayed as semi-transparent video
without effect on brightness and DC level adjustment.
Output Stage
The three output stages incorporate three functions
which are :
- The blanking stage : When high level is applied
to the BLK input (Pin 14), the three outputs are
switched to a voltage which is 400mV lower than
the BLACK level. The black level is the output
voltage with minimum brightness when input
signal video amplitude is equal to ”0”.
- The output stage itself : It is a large bandwidth
output amplifier which allow to deliver up to 5V
PP
on the three outputs (for 0.7V video signal on the
inputs). The typical bandwidth is 100MHz at -3dB
measured with 4V
PP
output signal on 12pF load.
Figure 3 :
Waveforms VOUT, BRT, CONT, OSD
HSYNC
BPCP
BLK
Video IN
FBLK
OSD IN
Data Transfer
The host MCU can write data into the TDA9206
registers. Read mode is not available.
To write data into the TDA9206, after a start, the
MCU must send (see Figure 5) :
- The I
2
C address slave byte with a low level for the
R/W bit.
- The byte of the internal register address where
the MCU wants to write data(s).
- The data.
All bytes are sent MSB bit first and the write data
transter is closed by a stop.
V
OUT1
, V
OUT2
, V
OUT3
V
CONT
(4)
V
OSD (5)
V
BRT (3)
V
BLACK
V
DC (1)
(2)
OSD
CONT
BRT
0.4V fixed
4/12
9206-06.EPS
Notes :
1.
2.
3.
4.
5.
V
DC
= 0.5 to 2.5V
V
BLACK
= V
DC
+ 0.4V
V
BRT
= V
BLACK
+ BRT (with BRT = 0 to 2.5V)
V
CONT
= V
BRT
+ CONT with CONT = k x Video IN (CONT = 5V
PP
max. for V
IN
= 0.7V
PP
)
V
OSD
= V
BRT
+ OSD with OSD = k1 x OSDIN (OSD max. = 5V
PP
, OSD min. = 312mV
PP
)
TDA9206
FUNCTIONAL DESCRIPTION
(continued)
Figure 4 :
Waveforms (DRIVE adjustment)
HSYNC
BPCP
BLK
Video IN
FBLK
OSD IN
V
OUT1
, V
OUT2
, V
OUT3
V
CONT
V
OS D
V
BRT
V
BLACK
V
DC
Two examples
of drive adjus tment
(1)
9206-07.EPS
Note :
1. Drive a djus tm ent modifies the following voltage s : V
CONT
, V
BRT
and V
O S D
.
Drive a djus tm ent do not modify the following voltage s : V
DC
a nd V
BLACK
.
Figure 5 :
I
2
C Write Operation
SCL
SDA
Start
I
2
C Slave Address
W
ACK
A7
A6
A5
A4
A3
A2
A1
A0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Stop
9206-08.EPS
9206-02.TBL
Register Address
Data Byte
QUICK REFERENCE DATA
Symbol
Parameter
Signal Bandwidth (2V
PP
/12pF load)
Rise and Fall Time (2V
PP
/12pF load)
Drive Adjustment Range on the 3 Channels separately
Maximum Output Voltage (V
IN
= 0.7 V
PP
)
Output Voltage Range (AC + DC)
Min.
Typ.
130
2.8
48
5
8
Max.
Unit
MHz
ns
dB
V
V
5/12
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