S25FL127SABNFI101 datasheet, PDF

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S25FL127SABNFI101: DescriptionFlash, 16MX8, PDSO8, WSON-8; Categorystorage storage; File Size2MB，142 Pages; ManufacturerCypress Semiconductor; Environmental Compliance

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Flash, 16MX8, PDSO8, WSON-8

S25FL127SABNFI101 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Cypress Semiconductor
package instruction	HVSON, SOLCC8,.25
Reach Compliance Code	compli
ECCN code	3A991.B.1.A
Maximum clock frequency (fCLK)	108 MHz
Data retention time - minimum	20
Durability	100000 Write/Erase Cycles
JESD-30 code	R-PDSO-N8
length	6 mm
memory density	134217728 bi
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of terminals	8
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	16MX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	HVSON
Encapsulate equivalent code	SOLCC8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3/3.3 V
Programming voltage	3 V
Certification status	Not Qualified
Maximum seat height	0.8 mm
Serial bus type	SPI
Maximum standby current	0.0003 A
Maximum slew rate	0.05 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
type	NOR TYPE
width	5 mm
write protect	HARDWARE

S25FL127SABNFI101 Preview

S25FL127S

128-Mbit (16 Mbyte)

3.0 V SPI Flash Memory

Features



CMOS 3.0 Volt Core



Density

– 128 Mbits (16 Mbytes)



Serial Peripheral Interface (SPI) with Multi-I/O

– SPI Clock polarity and phase modes 0 and 3

– Extended Addressing: 24- or 32-bit address options

– Serial Command set and footprint compatible with

S25FL-A,

S25FL-K, and S25FL-P SPI families

– Multi I/O Command set and footprint compatible with

S25FL-P SPI family



READ Commands

– Normal, Fast, Dual, Quad

– AutoBoot - power up or reset and execute a Normal or

Quad read command automatically at a preselected

address

– Common Flash Interface (CFI) data for configuration

information.



Programming (0.8 Mbytes/s)

– 256- or 512-byte Page Programming buffer options

– Quad-Input Page Programming (QPP) for slow clock

systems

– Automatic ECC -internal hardware Error Correction Code

generation with single bit error correction



Erase (0.5 Mbytes/s)

– Hybrid sector size option - physical set of sixteen 4-kbyte

sectors at top or bottom of address space with all

remaining sectors of 64 kbytes

– Uniform sector option - always erase 256-kbyte blocks for

software compatibility with higher density and future

devices.



Cycling Endurance

– 100,000 Program-Erase Cycles per sector, minimum



Data Retention

– 20 Year Data Retention, minimum



Security features

– One Time Program (OTP) array of 1024 bytes

– Block Protection:

– Status Register bits to control protection against

program or erase of a contiguous range of sectors.

– Hardware and software control options

– Advanced Sector Protection (ASP)

– Individual sector protection controlled by boot code or

password





Cypress 65 nm MirrorBit Technology with Eclipse



Architecture



Supply Voltage: 2.7V to 3.6V



Temperature Range:

– Industrial (-40°C to +85°C)

– Industrial Plus (-40°C to +105°C)

– Automotive AEC-Q100 Grade 3 (-40°C to +85°C)

– Automotive AEC-Q100 Grade 2 (-40°C to +105°C)



Packages (all Pb-free)

– 8-lead SOIC (208 mil)

– 16-lead SOIC (300 mil)

– 8-contact WSON 6 x 5 mm

– BGA-24 6 x 8 mm

– 5 x 5 ball (FAB024) and 4 x 6 ball (FAC024) footprint

options

– Known Good Die and Known Tested Die

Cypress Semiconductor Corporation

Document Number: 001-98282 Rev. *I

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised June 08, 2017

S25FL127S

Performance Summary

Maximum Read Rates

Command

Read

Fast Read

Dual Read

Quad Read

Clock Rate

(MHz)

108

Mbytes/s

6.25

13.5

Current Consumption

Operation

Serial Read 50 MHz

Serial Read 108 MHz

Quad Read 108 MHz

Program

Erase

Standby

kbytes/s

650

800

500

Current (mA)

16 (max)

24 (max)

47 (max)

50 (max)

0.07 (typ)

Typical Program and Erase Rates

Operation

Page Programming (256-byte page buffer)

Page Programming (512-byte page buffer)

4-kbyte Physical Sector Erase (Hybrid

Sector Option)

64-kbyte Physical Sector Erase (Hybrid

Sector Option)

256-kbyte Logical Sector Erase (Uniform

Sector Option)

Document Number: 001-98282 Rev. *I

Page 3 of 142

S25FL127S

Contents

Performance Summary

........................................................ 3

1.1

1.2

1.3

1.4

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

2.13

2.14

2.15

3.1

3.2

3.3

3.4

3.5

4.1

4.2

4.3

4.4

5.1

5.2

5.3

5.4

6.1

6.2

6.3

6.4

6.5

Overview

.......................................................................

General Description .......................................................

Migration Notes..............................................................

Glossary.........................................................................

Other Resources............................................................

7.1

7.2

7.3

7.4

7.5

7.6

8.1

8.2

8.3

8.4

9.1

9.2

9.3

9.4

9.5

9.6

9.7

9.8

9.9

9.10

Overview....................................................................... 47

Flash Memory Array...................................................... 47

ID-CFI Address Space .................................................. 48

JEDEC JESD216B Serial Flash Discoverable Parameters

(SFDP) Space............................................................... 48

OTP Address Space ..................................................... 49

Registers....................................................................... 50

Data Protection

........................................................... 59

Secure Silicon Region (OTP)........................................ 59

Write Enable Command................................................ 59

Block Protection ............................................................ 60

Advanced Sector Protection ......................................... 61

Commands

.................................................................. 66

Command Set Summary............................................... 67

Identification Commands .............................................. 72

Read Memory Array Commands .................................. 85

Program Flash Array Commands ................................. 93

Erase Flash Array Commands...................................... 97

One Time Program Array Commands ........................ 102

Advanced Sector Protection Commands .................... 103

Reset Commands ....................................................... 109

Embedded Algorithm Performance Tables ................. 110

Signal Descriptions

..................................................... 9

Input/Output Summary................................................... 9

Address and Data Configuration.................................. 10

Hardware Reset (RESET#).......................................... 10

Serial Clock (SCK) ....................................................... 10

Chip Select (CS#) ........................................................ 10

Serial Input (SI) / IO0 ................................................... 11

Serial Output (SO) / IO1............................................... 11

Write Protect (WP#) / IO2 ............................................ 11

Hold (HOLD#) / IO3 / RESET# .................................... 11

Voltage Supply (V

)................................................... 12

Supply and Signal Ground (V

) ................................. 12

Not Connected (NC) .................................................... 12

Reserved for Future Use (RFU)................................... 12

Do Not Use (DNU) ....................................................... 13

Block Diagrams............................................................ 13

Signal Protocols.........................................................

SPI Clock Modes .........................................................

Command Protocol ......................................................

Interface States............................................................

Configuration Register Effects on the Interface ...........

Data Protection ............................................................

Electrical Specifications............................................

Absolute Maximum Ratings .........................................

Operating Ranges........................................................

Power-Up and Power-Down ........................................

DC Characteristics .......................................................

Timing Specifications

................................................

Key to Switching Waveforms .......................................

AC Test Conditions ......................................................

Reset............................................................................

AC Characteristics .......................................................

Physical Interface

......................................................

SOIC 8-Lead Package .................................................

SOIC 16-Lead Package ...............................................

WSON 6 x 5 Package ..................................................

FAB024 24-Ball BGA Package ....................................

FAC024 24-Ball BGA Package ....................................

10. Data Integrity

............................................................. 112

10.1 Erase Endurance ........................................................ 112

10.2 Data Retention ............................................................ 112

11. Software Interface Reference

.................................. 113

11.1 Command Summary ................................................... 113

12.

12.1

12.2

12.3

12.4

12.5

13.

Serial Flash Discoverable Parameters (SFDP)

Address Map

............................................................. 115

SFDP Header Field Definitions ................................... 116

Device ID and Common Flash Interface (ID-CFI)

Address Map............................................................... 118

Device ID and Common Flash Interface (ID-CFI) ASO Map

— Automotive Only ..................................................... 133

Registers..................................................................... 134

Initial Delivery State .................................................... 137

Ordering Information

................................................ 138

Address Space Maps

................................................. 47

14. Revision History........................................................

140

Sales, Solutions, and Legal Information .................... 142

Worldwide Sales and Design Support .......................... 142

Products ....................................................................... 142

PSoC® Solutions ......................................................... 142

Cypress Developer Community .................................... 142

Technical Support ........................................................ 142

Document Number: 001-98282 Rev. *I

Page 3 of 142

S25FL127S

1. Overview

1.1



General Description

MirrorBit technology - that stores two data bits in each memory array transistor

Eclipse architecture - that dramatically improves program and erase performance

65 nm process lithography

The Cypress S25FL127S device is a flash non-volatile memory product using:

This device connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (Single

I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands. This multiple

width interface is called SPI Multi-I/O or MIO.

The Eclipse architecture features a Page Programming Buffer that allows up to 128 words (256 bytes) or 256 words (512 bytes) to

be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase

algorithms.

Executing code directly from flash memory is often called Execute-In-Place or XIP. By using FL-S devices at the higher clock rates

supported, with QIO command, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous,

NOR flash memories while reducing signal count dramatically.

The S25FL127S product offers a high density coupled with the flexibility and fast performance required by a variety of embedded

applications. It is ideal for code shadowing, XIP, and data storage.

Document Number: 001-98282 Rev. *I

Page 4 of 142

S25FL127S

1.2

1.2.1

Migration Notes

Features Comparison

The S25FL127S device is command set and footprint compatible with prior generation FL-K, FL-P, and FL-S family devices.

Table 1. FL Generations Comparison

Parameter

Technology Node

Architecture

Density

Bus Width

Supply Voltage

Normal Read Speed

(SDR)

Fast Read Speed (SDR)

Dual Read Speed (SDR)

Quad Read Speed

(SDR)

Fast Read Speed (DDR)

Dual Read Speed (DDR)

Quad Read Speed

(DDR)

Program Buffer Size

Uniform Sector Size

Parameter Sector Size

Number of Parameter

Sector

Sector Erase Rate (typ.)

Page Programming Rate

(typ.)

OTP

Advanced Sector

Protection

Auto Boot Mode

Erase Suspend/Resume

Program Suspend/

Resume

Operating Temperature

FL-K

90 nm

Floating Gate

4 Mb - 128 Mb

x1, x2, x4

2.7V - 3.6V

6 MB/s (50 MHz)

13 MB/s (104 MHz)

26 MB/s (104 MHz)

52 MB/s (104 MHz)

256B

4 kB

N/A

135 kB/s (4 kB), 435 kB/s

(64 kB)

365 kB/s (256B)

768B (3 x 256B)

Yes

-40°C to +85°C

FL-P

90 nm

MirrorBit

32 Mb - 256 Mb

x1, x2, x4

2.7V - 3.6V

5 MB/s (40 MHz)

13 MB/s (104 MHz)

20 MB/s (80 MHz)

40 MB/s (80 MHz)

256B

64 kB / 256 kB

4 kB

130 kB/s (64 kB)

170 kB/s (256B)

506B

FL-S

65 nm

MirrorBit Eclipse

128 Mb, 256 Mb, 512

Mb, 1 Gb

x1, x2, x4

2.7V - 3.6V / 1.65V -

3.6V V

6 MB/s (50 MHz)

17 MB/s (133 MHz)

26 MB/s (104 MHz)

52 MB/s (104 MHz)

16 MB/s (66 MHz)

33 MB/s (66 MHz)

66 MB/s (66 MHz)

256B / 512B

64 kB / 256 kB

4 kB (option)

32 (option)

FL127S

65 nm

MirrorBit Eclipse

128 Mb

x1, x2, x4

2.7V - 3.6V

6 MB/s (50 MHz)

13.5 MB/s (108 MHz)

27 MB/s (108 MHz)

54 MB/s (108 MHz)

256B / 512B

64 kB / 256 kB

4 kB (option)

16 (option)

30 kB/s (4 kB), 500 kB/s 30 kB/s (4 kB), 500 kB/s

(64 kB / 256 kB)

1000 kB/s (256B),

1500 kB/s (512B)

1024B

Yes

650 kB/s (256B),

800 kB/s (512B)

1024B

Yes

-40°C to +85°C / +105°C -40°C to +85°C / +105°C -40°C to +85°C / +105°C

Notes:

1. 256B program page option only for 128 Mb and 256-Mb density FL-S devices.

2. FL-P column indicates FL129P MIO SPI device (for 128-Mb density). FL128P does not support MIO, OTP or 4-kB sectors.

3. 64-kB sector erase option only for 128-Mb/256-Mb density FL-P and FL-S devices.

4. FL-K family devices can erase 4-kB sectors in groups of 32 kB or 64 kB.

5. Refer to individual data sheets for further details.

Document Number: 001-98282 Rev. *I

Page 5 of 142

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S25FL127SABNFI101 Related Products

	S25FL127SABNFI101	S25FL127SABMFI103	S25FL127SABNFI100
Description	Flash, 16MX8, PDSO8, WSON-8	Flash, 16MX8, PDSO8, SOIC-8	Flash, 16MX8, PDSO8, WSON-8
Is it Rohs certified?	conform to	conform to	conform to
Maker	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor
package instruction	HVSON, SOLCC8,.25	SOP, SOP8,.3	HVSON, SOLCC8,.25
Reach Compliance Code	compli	compliant	compli
Maximum clock frequency (fCLK)	108 MHz	108 MHz	108 MHz
Data retention time - minimum	20	20	20
Durability	100000 Write/Erase Cycles	100000 Write/Erase Cycles	100000 Write/Erase Cycles
JESD-30 code	R-PDSO-N8	S-PDSO-G8	R-PDSO-N8
length	6 mm	5.283 mm	6 mm
memory density	134217728 bi	134217728 bit	134217728 bi
Memory IC Type	FLASH	FLASH	FLASH
memory width	8	8	8
Number of functions	1	1	1
Number of terminals	8	8	8
word count	16777216 words	16777216 words	16777216 words
character code	16000000	16000000	16000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C
organize	16MX8	16MX8	16MX8
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	HVSON	SOP	HVSON
Encapsulate equivalent code	SOLCC8,.25	SOP8,.3	SOLCC8,.25
Package shape	RECTANGULAR	SQUARE	RECTANGULAR
Package form	SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE	SMALL OUTLINE	SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
Parallel/Serial	SERIAL	SERIAL	SERIAL
power supply	3/3.3 V	3/3.3 V	3/3.3 V
Programming voltage	3 V	3 V	3 V
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	0.8 mm	2.159 mm	0.8 mm
Serial bus type	SPI	SPI	SPI
Maximum standby current	0.0003 A	0.0001 A	0.0003 A
Maximum slew rate	0.05 mA	0.063 mA	0.05 mA
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V
Nominal supply voltage (Vsup)	3 V	3 V	3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	NO LEAD	GULL WING	NO LEAD
Terminal pitch	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL
type	NOR TYPE	NOR TYPE	NOR TYPE
width	5 mm	5.283 mm	5 mm
write protect	HARDWARE	HARDWARE/SOFTWARE	HARDWARE
ECCN code	3A991.B.1.A	-	3A991.B.1.A
Output characteristics	3-STATE	-	3-STATE

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