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70V3569S5DR

Description
PQFP-208, Tray
Categorystorage    storage   
File Size463KB,18 Pages
ManufacturerIDT (Integrated Device Technology)
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70V3569S5DR Overview

PQFP-208, Tray

70V3569S5DR Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codePQFP
package instructionQFP, QFP208,1.2SQ,20
Contacts208
Manufacturer packaging codeDR208
Reach Compliance Code_compli
ECCN code3A991.B.2.B
Maximum access time5 ns
Other featuresPIPELINED OUTPUT MODE, SELF TIMED WRITE CYCLE
Maximum clock frequency (fCLK)100 MHz
I/O typeCOMMON
JESD-30 codeS-PQFP-G208
JESD-609 codee0
memory density589824 bi
Memory IC TypeDUAL-PORT SRAM
memory width36
Humidity sensitivity level3
Number of functions1
Number of ports2
Number of terminals208
word count16384 words
character code16000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize16KX36
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Encapsulate equivalent codeQFP208,1.2SQ,20
Package shapeSQUARE
Package formFLATPACK
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply2.5/3.3,3.3 V
Certification statusNot Qualified
Maximum standby current0.015 A
Minimum standby current3.15 V
Maximum slew rate0.36 mA
Maximum supply voltage (Vsup)3.45 V
Minimum supply voltage (Vsup)3.15 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
HIGH-SPEED 3.3V 16K x 36
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
70V3569S
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 4.2/5/6ns (max.)
– Industrial: 5ns (max)
Pipelined output mode
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
– Fast 4.2ns clock to data out
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
address inputs @ 133MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, single 3.3V (±150mV) power supply for
core
LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os and control signals on each port
Industrial temperature range (-40°C to +85°C) is
available for selected speeds
Available in a 208-pin Plastic Quad Flatpack (PQFP),
208-ball fine-pitch Ball Grid Array, and 256-pin Ball
Grid Array
Green parts available, see ordering instructions
Functional Block Diagram
BE
3L
BE
3R
BE
2L
BE
1L
BE
0L
BE
2R
BE
1R
BE
0R
R/W
L
B B
WW
0 1
L L
B B
WW
2 3
L L
B BB B
W WW W
3 2 1 0
R RR R
R/W
R
CE
0L
CE
1L
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
OE
R
16K x 36
MEMORY
ARRAY
I/O
0L
- I/O
35L
Din_L
Din_R
I/O
0R
- I/O
35R
CLK
L
A
13L
A
0L
CNTRST
L
ADS
L
CNTEN
L
CLK
R
,
Counter/
Address
Reg.
A
13R
ADDR_L
ADDR_R
Counter/
Address
Reg.
A
0R
CNTRST
R
ADS
R
CNTEN
R
4831 tbl 01
AUGUST 2019
1
©2019 Integrated Device Technology, Inc.
DSC 4831/15

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