Fe m toCloc k
®
Crys t a l-t o -LVDS
8-Output Clock Synthesizer
Datasheet
814S208
General Description
The 814S208 is an eight LVDS output clock synthesizer designed for
wireless infrastructure applications. The device generates eight
copies of a selectable 122.88MHz or 153.6MHz clock signal with
excellent phase jitter performance. The PLL is optimized for a
reference frequency of 30.72MHz. Both a crystal interface and a
differential system clock input are supported for the reference
frequency. An extra LVDS output duplicates the reference frequency
and is provided for clock tree cascading. The device uses IDT’s third
generation FemtoClock® technology for an optimum of high clock
frequency and low phase noise performance, combined with a low
power consumption. A PLL lock status output is provided for
monitoring and diagnosis purpose. The device supports a 3.3V
voltage supply and is packaged in a small, lead-free (RoHS 6)
48-lead VFQFN package. The extended temperature range supports
wireless infrastructure, telecommunication and networking end
equipment requirements.
Features
•
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Third generation FemtoClock® technology
Selectable 122.88MHz or 153.6MHz output clock synthesized
from a 30.72MHz fundamental mode crystal
Eight differential LVDS clock outputs
Differential reference clock input pair
PLL lock indicator output
Crystal interface designed for a 30.72MHz,
parallel resonant crystal
RMS phase jitter @ 122.88MHz, using a 30.72MHz crystal
(12kHz - 20MHz): 0.650ps (typical)
RMS phase jitter @ 153.6MHz, using a 30.72MHz crystal
(12kHz - 20MHz): 0.642ps (typical)
LVCMOS interface levels for the control input
Full 3.3V supply voltage
Available in Lead-free (RoHS 6) 48-lead VFQFN package
-40°C to 85°C ambient operating temperature
Block Diagram
nOE_A
XTAL_IN
OSC
XTAL_OUT
REF_CLK
nREF_CLK
REF_SEL
BW[1:0]
BYPASS
N_SEL
nOE_B0
nOE_B1
nOE_B2
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown (2)
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
1
0
Pulldown
QLOCK
1
f
REF
QA
nQA
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
QB4
nQB4
QB5
nQB5
QB6
nQB6
QB7
nQB7
PFD
&
LPF
FemtoClock®
VCO
570MHz - 640MHz
÷20
÷20
0
N
÷5,
÷4
2
©2016 Integrated Device Technology, Inc.
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Revision C, April 7, 2016
814S208 Datasheet
Pin Assignment
REF_SEL
BYPASS
nOE_B0
nOE_B1
nOE_B2
48 47 46 45 44 43 42 41 40 39 38 37
XTAL_IN
XTAL_OUT
VDD
REF_CLK
nREF_CLK
GND
VDDOL
QLOCK
GND
QA
nQA
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
36
35
34
33
32
31
30
29
28
27
26
25
VDD
nQB7
QB7
nQB6
QB6
GND
VDD
nQB5
QB5
nQB4
QB4
GND
GND
nQB0
nQB1
GND
QB0
QB1
QB2
nQB2
QB3
nQB3
VDD
814S208
48-lead VFQFN
7.0mm x 7.0mm x 0.925mm, package body
K Package
Top View
©2016 Integrated Device Technology, Inc.
VDD
nOE_A
N_SEL
VDDA
GND
GND
BW1
BW0
2
Revision C, April 7, 2016
814S208 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1,
2
3, 12, 18,
24, 30, 36
4
5
6, 9, 13, 19,
25, 31, 41, 48
7
8
10, 11
14, 15
16, 17
20, 21
22, 23
26, 27
28, 29
32, 33
34, 35
37
38,
39,
45
40
42
43, 44
46
47
Name
XTAL_IN,
XTAL_OUT
V
DD
REF_CLK
nREF_CLK
GND
V
DDOL
QLOCK
QA, nQA
QB0, nQB0
QB1, nQB1
QB2, nQB2
QB3, nQB3
QB4, nQB4
QB5, nQB5
QB6, nQB6
QB7, nQB7
nOE_A
nOE_B2,
nOE_B1,
nOE_B0
N_SEL
V
DDA
BW0, BW1
BYPASS
REF_SEL
Input
Power
Input
Input
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Pulldown
Pulldown
Pullup/
Pulldown
Type
Description
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Core power supply pins.
Non-inverting differential reference clock input. Differential output can accept the
following differential input levels: LVPECL, LVDS, CML.
Inverting differential reference clock input. Differential output can accept the
following differential input levels: LVPECL, LVDS, CML.
Power supply ground.
Output supply pin for the PLL lock output (QLOCK). Supports 3.3V, 2.5V or 1.8V.
PLL lock indication. See Table 3I for function. Supports 3.3V, 2.5V or 1.8V.
Differential clock output pair. LVDS interface levels.
Differential clock output pair. LVDS interface levels
Differential clock output pair. LVDS interface levels
Differential clock output pair. LVDS interface levels
Differential clock output pair. LVDS interface levels
Differential clock output pair. LVDS interface levels
Differential clock output pair. LVDS interface levels
Differential clock output pair. LVDS interface levels
Differential clock output pair. LVDS interface levels
Output enable input. See Table 3E for function.
LVCMOS/LVTTL interface levels.
Output enable inputs. See Tables 3F-3H for function.
LVCMOS/LVTTL interface levels.
Frequency select pin. See Table 3A for function.
LVCMOS/LVTTL interface levels.
Analog power supply.
Pulldown
Pulldown
Pulldown
PLL bandwidth control pins. See Table 3D for function.
LVCMOS/LVTTL interface levels.
PLL bypass mode select pin. See Table 3B for function.
LVCMOS/LVTTL interface levels.
Reference select input. See Table 3C for function.
LVCMOS/LVTTL interface levels.
Input
Pulldown
Input
Power
Input
Input
Input
Pulldown
NOTE:
Pulldown and Pullup
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
©2016 Integrated Device Technology, Inc.
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Revision C, April 7, 2016
814S208 Datasheet
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
QLOCK = HIGH, V
DDOL
= 3.3V
R
OUT
Output
Impedance
QLOCK
QLOCK = HIGH, V
DDOL
= 2.5V
QLOCK = HIGH, V
DDOL
= 1.8V
QLOCK = LOW, V
DDOL
= 3.3V, 2.5V, 1.8V
Test Conditions
Minimum
Typical
2
51
51
26
32
44
22
Maximum
Units
pF
k
k
Function Tables
Table 3A. Output Divider N Function Table
Inputs
N_SEL
0 (default)
1
N
÷5
÷4
Operation
QB[0:7] Frequency with f
REF
= 30.72MHz
122.88MHz, (4 * f
REF
)
153.6MHz, (5 * f
REF
)
NOTE: N_SEL is an asynchronous control.
NOTE: With f
XTAL
= 30.72MHz and all control inputs in the default state, the ICS814S208I generates 30.72MHz at the QA output and
122.88MHz at the QBx outputs.
Table 3B. PLL BYPASS Function Table
Input
BYPASS
0 (default)
1
Operation
QA
f
OUT,
QA = f
VCO
÷ 20
f
OUT,
QA = f
REF
(PLL bypass)
QB[0:7]
f
OUT,
QBx = f
REF
* 20 ÷ N
NOTE: BYPASS is an asynchronous control.
NOTE: In PLL bypass mode, the frequency f
REF
is output at QA without frequency division. AC specifications do not apply in PLL bypass
mode.
Table 3C. PLL Reference Clock Select Function Table
Input
REF_SEL
0 (default)
1
Operation
The crystal interface is selected as reference clock
The REF_CLK input is selected as reference clock
NOTE: REF_SEL is an asynchronous control.
©2016 Integrated Device Technology, Inc.
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Revision C, April 7, 2016
814S208 Datasheet
Table 3D. PLL Bandwidth Function Table
Inputs
BW1
0 (default)
0 (default)
1
1
BW0
0 (default)
1
0 (default)
1
Operation
PLL Bandwidth
240kHz
520kHz
1MHz
2MHz
NOTE: BW[1:0] is an asynchronous control.
NOTE: With the lowest PLL bandwidth setting (BW[1:0] = 00, 240kHz), the PLL attenuates input reference jitter with spectral components
above 240kHz. With the highest PLL bandwidth setting (BW[1:0] = 11, 2MHz), the PLL is not optimized for input reference jitter attenuation.
Table 3E. nOE_A Output Enable Function Table
Input
nOEA
0 (default)
1
Operation
QA, nQA outputs are enabled
QA, nQA outputs are disabled (high-impedance)
Table 3I. QLOCK Output Function Table
Output
QLOCK
0
1
PLL Status
The PLL is locked to the input reference clock
The PLL is not locked to the input reference clock
NOTE: nOE_A is an asynchronous control.
NOTE: QLOCK supports 3.3V, 2.5V or 1.8V according to the voltage
supplied at V
DDOL
. See Table 4B.
Table 3F. nOE_B0 Output Enable Function Table
Input
nOE_B0
0 (default)
1
Operation
QB[0:3], nQB[0:3] outputs are enabled
QB[0:3]. nQB[0:3] outputs are disabled (high-impedance)
NOTE: nOE_B0 is an asynchronous control.
Table 3G. nOE_B1 Output Enable Function Table
Input
nOE_B1
0 (default)
1
Operation
QB[4:5], nQB[4:5] outputs are enabled
QB[4:5], nQB[4:5] outputs are disabled (high-impedance)
NOTE: nOE_B1 is an asynchronous control.
Table 3H. nOE_B2 Output Enable Function Table
Input
nOE_B2
0 (default)
1
Operation
QB[6:7], nQB[6:7] outputs are enabled
QB[6:7], nQB[6:7] outputs are disabled (high-impedance)
NOTE: nOE_B2 is an asynchronous control.
©2016 Integrated Device Technology, Inc.
5
Revision C, April 7, 2016
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