FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-
LVDS/LVCMOS FREQUENCY SYNTHESIZER
ICS8440259D-05
G
ENERAL
D
ESCRIPTION
The ICS8440259D-05 is a 9 output synthesizer
optimized to generate Gigabit and 10 Gigabit Ether-
HiPerClockS™
net clocks and is a member of the HiPerClockS™
family of high performance clock solutions from IDT.
Using a 25MHz, 18pF parallel resonant crystal, the
device will generate 125MHz and 3.90625MHz clocks with mix-
ed LVDS and LVCMOS/LVTTL output levels. The ICS8440259D-
05 uses IDT’s 3
rd
generations low phase noise VCO technology
and can achieve <1ps typical rms phase jitter, easily meeting
Ethernet jitter requirements. The ICS8440259D-05 is packaged
in a small, 32-pin VFQFN package that is optimum for applications
with space limitations.
F
EATURES
•
Five differential LVDS outputs at 125MHz
Three LVCMOS/LVTTL single-ended outputs at 125MHz
One LVCMOS/LVTTL single-ended output at 3.90625MHz
•
Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input and PLL bypass from a single select pin
•
VCO range: 510MHz - 650MHz
•
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.41ps (typical), LVDS output
•
Full 3.3V supply mode
•
0°C to 70°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
B
LOCK
D
IAGRAM
nPLL_BYPASS
Pullup
REF_CLK
Pulldown
25MHz
0
0
Q0
nQ0
Q1
nQ1
Q2
XTAL_IN
Phase
Detector
1
VCO
490-680MHz
÷5
1
OSC
XTAL_OUT
P
IN
A
SSIGNMENT
XTAL_OUT
REF_CLK
XTAL_IN
GND
V
DD
nc
32 31 30 29 28 27 26 25
Q4
Q0
nQ0
GND
Q1
nQ1
V
DDO
_
LVDS
Q2
nQ2
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
V
DDO
_
LVDS
GND
nQ4
GND
nQ3
V
DD
Q3
Q4
ICS8440259D-05
32-Lead VFQFN
5mm x 5mm x 0.925mm
package body
K Package
Top View
IDT
™
/ ICS
™
LVDS/LVCMOS FREQUENCY SYNTHESIZER
nPLL_BYPASS
÷25
V
DDA
nQ2
Q3
nQ3
24
23
22
21
20
19
18
17
Q8
V
DDO
_
LVCMOS
Q7
GND
Q6
V
DDO
_
LVCMOS
Q5
GND
Q7
Q6
Q5
nQ4
÷32
Q8
1
ICS8440259DK-05 REV. A NOVEMBER 24, 2008
ICS8440259D-05
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 9, 15,
17, 21, 32
4, 5
6, 12
7, 8
10, 11
13, 14
16, 27
18, 20,
22, 24
19, 23
25
Name
Q0, nQ0
GND
Q1, nQ1
V
DDO_LVDS
Q2, nQ2
Q3, nQ3
Q4, nQ4
V
DD
Q5, Q6,
Q7, Q8
V
DDO_LVCMOS
V
DDA
Type
Output
Power
Output
Power
Output
Output
Output
Power
Output
Power
Power
Description
Differential clock outputs. LVDS interface levels.
Power supply ground.
Differential clock outputs. LVDS interface levels.
Output supply pins for Q[0:4]/nQ[0:4] LVDS outputs.
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
Core supply pins.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Output supply pins for Q5:Q8 LVCMOS outputs.
Analog supply pin.
Input select and PLL bypass control pin. See Table 3.
26
nPLL_BYPASS
Input
Pullup
LVCMOS/LVTTL interface levels.
28
nc
Unused
No connect.
Single-ended reference clock input. Only selected in nPLL_BYPASS
29
REF_CLK
Input
Pulldown
mode. LVCMOS/LVTTL interface levels.
30,
XTAL_IN,
Crystal oscillator interface. XTAL_OUT is the output.
Input
31
XTAL_OUT
XTAL_IN is the input.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pulldown Resistor
Output Impedance
Q5:Q8
V
DD,
V
DDO_LVCMOS
= 3.465V
Test Conditions
Minimum
Typical
4
15
51
25
Maximum
Units
pF
pF
kΩ
Ω
T
ABLE
3. PLL B
YPASS AND
I
NPUT
S
ELECT
F
UNCTION
T
ABLE
nPLL_BYPASS
0
1
Inputs
PLL Bypass
PLL Bypassed
PLL Enabled
Input Selected
REF_CLK
XTAL_IN/XTAL_OUT (default)
IDT
™
/ ICS
™
LVDS/LVCMOS FREQUENCY SYNTHESIZER
2
ICS8440259DK-05 REV. A NOVEMBER 24, 2008
ICS8440259D-05
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVCMOS)
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Operating Temperature Range, T
A
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
10mA
15mA
-40°C to +85°C
-65°C to 150°C
37°C/W (0 mps)
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO_LVCMOS
+ 0.5V
NOTE:
Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
ratings are stress specifications only. Functional operation of
product at these conditions or any conditions beyond those listed
in the
DC Characteristics
or
AC Characteristics
is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO_LVCMOS
= V
DDO_LVDS
= 3.3V ± 5%,T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO_LVCMOS,
V
DDO_LVDS
I
DD
I
DDA
I
DDO_LVCMOS
I
DDO_LVDS
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
LVCMOS Output Supply Current
LVDS Output Supply Current
Output Not Loaded
Output Not Loaded
Output Not Loaded
Output Not Loaded
Test Conditions
Minimum
3.135
V
DD
– 0.40
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
120
40
20
165
Units
V
V
V
mA
mA
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDO_LVCMOS
= 3.3V ± 5%,T
A
= 0°C
TO
70°C
Symbol Parameter
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
REF_CLK
nPLL_BYPASS
REF_CLK
nPLL_BYPASS
Q5:Q8
Q5:Q8
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
I
OH
= -12mA
I
OL
= 12mA
-5
-150
2.6
0.5
Test Conditions
Minimum Typical
2
-0.3
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
V
V
IDT
™
/ ICS
™
LVDS/LVCMOS FREQUENCY SYNTHESIZER
3
ICS8440259DK-05 REV. A NOVEMBER 24, 2008
ICS8440259D-05
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
T
ABLE
4C. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDO_LVDS
= 3.3V ± 5%,T
A
= 0°C
TO
70°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.25
1.35
Test Conditions
Minimum
300
Typical
400
Maximum
545
50
1.50
50
Units
mV
mV
V
mV
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant cr ystal.
Test Conditions
Minimum
Typical
25
50
7
1
Maximum
Units
MHz
Ω
pF
mW
Fundamental
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= V
DDO_LVCMOS
= V
DDO_LVDS
= 3.3V ± 5%,T
A
= 0°C
TO
70°C
Symbol
f
OUT
Parameter
Output
Frequency
RMS Phase Jitter
(Random);
NOTE 1
Q0/nQ0:Q4/nQ4
Q5:Q7
Q8
Q0:4/nQ0:4
Q5:Q7
Q0/nQ0:Q4/nQ4
(NOTE 2)
Q0/nQ0:Q4/nQ4
Q5:Q7
Q8 (NOTE 2)
odc
Output
Duty Cycle
Q0/nQ0:Q4/nQ4
125MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
125MHz, 20% to 80%
125MHz, 20% to 80%
125MHz, 20% to 80%
3.90625MHz, 20% to 80%
125MHz
0. 5
0.4
0.35
1.0
45
Test Conditions
Minimum
Typical
125
125
3.90625
0.44
0.41
1.20
0.65
1.20
1.65
55
Maximum
Units
MHz
MHz
MHz
ps
ps
ns
ns
ns
ns
%
t
jit(Ø)
t
R
/ t
F
Output
Rise/Fall Time
Q5:Q7
125MHz
42
58
%
Q8
3.90625MHz
49
51
%
Q0/nQ0:Q4/nQ4
125MHz
47
53
%
Output
odc
Duty Cycle,
Q5:Q7
125MHz
43
57
%
BYPASS Mode
Q8
3.90625MHz
49
51
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditons.
NOTE: T
A
, Ambient Temperature applied using forced air flow.
NOTE 1: Please refer to the Phase Noise Plots.
NOTE 2: Output loaded with 15pF.
IDT
™
/ ICS
™
LVDS/LVCMOS FREQUENCY SYNTHESIZER
4
ICS8440259DK-05 REV. A NOVEMBER 24, 2008
ICS8440259D-05
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
T
YPICAL
P
HASE
N
OISE AT
125MH
Z
(LVCMOS @ 3.3V)
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.41ps (typical)
➤
Ethernet Filter
N
OISE
P
OWER
dBc
Hz
Raw Phase Noise Data
➤
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.44ps (typical)
T
YPICAL
P
HASE
N
OISE AT
125MH
Z
(LVDS @ 3.3V)
➤
Ethernet Filter
Phase Noise Result by adding
Ethernet Filter to raw data
➤
Phase Noise Result by adding
Ethernet Filter to raw data
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
OWER
dBc
Hz
Raw Phase Noise Data
O
FFSET
F
REQUENCY
(H
Z
)
IDT
™
/ ICS
™
LVDS/LVCMOS FREQUENCY SYNTHESIZER
➤
➤
5
ICS8440259DK-05 REV. A NOVEMBER 24, 2008
京公网安备 11010802033920号
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