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8735BMI-21LF

Description
SOIC-20, Tube
Categorylogic    logic   
File Size603KB，19 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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8735BMI-21LF Overview

SOIC-20, Tube

8735BMI-21LF Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeSOIC
package instructionSOIC-20
Contacts20
Manufacturer packaging codePSG20
Reach Compliance Codecompli
ECCN codeEAR99
Samacsys DescriptiSOIC 300 MIL
series8735
Input adjustmentDIFFERENTIAL MUX
JESD-30 codeR-PDSO-G20
JESD-609 codee3
length12.8 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Humidity sensitivity level1
Number of functions1
Number of inverted outputs
Number of terminals20
Actual output times4
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)4.9 ns
Same Edge Skew-Max（tskwd）0.035 ns
Maximum seat height2.65 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.5 mm
minfmax700 MHz

8735BMI-21LF Preview

700MHz, Differential-to-3.3V LVPECL
Zero Delay Clock Generator
8735BI-21
DATA SHEET
General Description
The 8735BI-21 is a highly versatile 1:1 Differential-to-3.3V LVPECL
clock generator. The CLK, nCLK pair can accept most standard
differential input levels. The 8735BI-21 has a fully integrated PLL and
can be configured as zero delay buffer, multiplier or divider, and has
an output frequency range of 31.25MHz to 700MHz. The reference
divider, feedback divider and output divider are each programmable,
thereby allowing for the following output-to-input frequency ratios:
8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the
device to achieve “zero delay” between the input clock and the output
clocks. The PLL_SEL pin can be used to bypass the PLL for system
test and debug purposes. In bypass mode, the reference clock is
routed around the PLL and into the internal output dividers.
Features
• One differential 3.3V LVPECL output pair, one differential feedback
output pair
• Differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential input levels:
LVDS, LVPECL, LVHSTL, HCSL
• Output frequency range: 31.25MHz to 700MHz
• Input frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• External feedback for “zero delay” clock regeneration with
configurable frequencies
20
19
18
17
16
15
14
13
12
11
Pin Assignment
CLK
nCLK
MR
V
CC
nFB_IN
FB_IN
SEL2
V
EE
nQFB
QFB
1
2
3
4
5
6
7
8
9
10
nc
SEL1
SEL0
V
CC
PLL_SEL
V
CCA
SEL3
V
CCO
Q
nQ
• Cycle-to-cycle jitter: 50ps (maximum)
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in RoHS compliant package
Block Diagram
PLL_SEL
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
8735BI-21
20-pin, 7.5mm x 12.8mm X 2.3MM SOIC Package
PLL_SEL
SEL3
CLK
nCLK
0
1
Q
nQ
QFB
nQFB
V
CCA
V
CC
V
EE
nc
nc
32
31
30
29
 
nc
PLL
8:1,
4:1, 2:1, 1:1,
1:2, 1:4, 1:8
28
27
26
25
24
23
22
21
SEL0
SEL1
nc
nc
CLK
nCLK
nc
MR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
CCO
nc
Q
nQ
QFB
nQFB
nc
V
cco
FB_IN
nFB_IN
8735BI-21
SEL0
SEL1
SEL2
SEL3
MR
20
19
18
17
V
CC
nFB_IN
FB_IN
SEL2
V
EE
nc
nc
32-pin, 5mm x 5mm X 0.925MM VFQFN Package
8735BI-21 REVISION 1 1/27/15
nc
1
©2015 Integrated Device Technology, Inc.
8735BI-21 DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
1
Name
CLK
nCLK
nFB_IN
FB_IN
MR
SEL0, SEL1,
SEL2, SEL3
PLL_SEL
nQ, Q
nQFB, QFB
V
EE
V
CC
V
CCA
V
CCO
Input
Input
Input
Input
Input
Type
Pulldown
Pullup
Pullup
Pulldown
Pulldown
Description
Non-inverting differential clock input.
Inverting differential clock input.
Feedback input to phase detector for regenerating clocks with “zero delay”. Connect to nQFB.
Feedback input to phase detector for regenerating clocks with “zero delay”. Connect to QFB.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the
true outputs Q and QFB to go low and the inverted outputs nQ and nQFB to go high. When
LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels.
Determines output divider values in Table 3.
LVCMOS / LVTTL interface levels.
Selects between the PLL and reference clock as the input to the dividers. When LOW,
selects reference clock. When HIGH, selects PLL.
LVCMOS / LVTTL interface levels.
Differential feedback outputs. LVPECL interface levels.
Differential feedback outputs. LVPECL interface levels.
Negative supply.
Core supply.
Analog supply.
Output supply.
Input
Pulldown
Input
Output
Output
Power
Power
Power
Power
Pullup
NOTE 1:
Pullup
and
Pulldown
refer to internal input resistors. See
Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
IN, nIN
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY
CLOCK GENERATOR
2
REVISION 1 1/27/15
8735BI-21 DATA SHEET
Table
3A.
Control Input Function Table
1
Outputs
PLL_SEL = 1
PLL Enable Mode
Reference Frequency Range (MHz)
250-700
125 - 350
62.5 - 175
31.25 - 87.5
250 - 700
125 - 350
62.5 - 175
250 - 700
125 - 350
250 - 700
125 - 350
62.5 - 175
31.25 - 87.5
62.5 - 175
31.25 - 87.5
31.25 - 87.5
Q, nQ; QFB, nQFB
÷ 1 (default)
÷1
÷1
÷1
÷2
÷2
÷2
÷4
÷4
÷8
x2
x2
x2
x4
x4
x8
Inputs
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
NOTE 1: VCO frequency range for all configurations above is 250MHz to 700MHz.
Table
3B.
PLL Bypass Function Table
1
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Q, nQ; QFB, nQFB
÷ 4 (default)
÷4
÷4
÷8
÷8
÷8
÷ 16
÷ 16
÷ 32
÷ 64
÷2
÷2
÷4
÷1
÷2
÷1
Inputs
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
NOTE 1: VCO frequency range for all configurations above is 250MHz to 700MHz.
REVISION 1 1/27/15
3
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY
CLOCK GENERATOR
8735BI-21 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Electrical
Characteristics”
or
AC Electrical Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
Item
Supply Voltage, V
CC_X
Inputs, V
CC
Outputs, V
CCO
Junction Temperature, T
J
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
-0.5V to V
CCO
+ 0.5V
125°C
-65C to 150C
DC Electrical Characteristics
Table 4A. Power
Supply
DC Characteristics,
V
CC
= V
CCO
= 3.3V ±5%, T
A
= -40°C to 85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
155
17
Units
V
V
V
mA
mA
Table 4B. LVCMOS/LVTTL Input DC Characteristics,
V
CC
= V
CCO
= 3.3V ±5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input High
Current
SEL0, SEL1,
SEL2, SEL3, MR
PLL_SEL
SEL0, SEL1,
SEL2, SEL3, MR
PLL_SEL
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
I
IL
Input Low
Current
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY
CLOCK GENERATOR
4
REVISION 1 1/27/15
8735BI-21 DATA SHEET
Table 4C. Differential Input DC Characteristics,
V
CC
= V
CCO
= 3.3V ±5%, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High
Current
Input Low
Current
CLK, FB_IN
nCLK, nFB_IN
CLK, FB_IN
nCLK, nFB_IN
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
0.15
V
EE
+ 0.5V
1.3
V
CC
– 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Voltage
1
Common Mode Input Voltage
2, 3
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
NOTE 3: For single ended applications, the maximum input voltage for CLK, nCLK is V
CC
+ 0.3V.
Table 4D. LVPECL DC Characteristics,
V
CC
= V
CCO
= 3.3V ±5%, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage
1
Output Low Voltage
1
Peak-to-Peak Voltage Swing
Test Conditions
Minimum
V
CCO
– 1.4
V
CCO
– 2.1
0.6
Typical
Maximum
V
CCO
– 0.9
V
CCO
– 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
to V
CCO
– 2V.
Table 5. Input Frequency Characteristics,
V
CC
= V
CCO
= 3.3V ±5%, T
A
= 0°C to 85°C
Symbol
f
IN
Parameter
Input Frequency
CLK, nCLK
Test Conditions
PLL_SEL = 1
PLL_SEL = 0
Minimum
31.25
Typical
Maximum
700
700
Units
MHz
MHz
REVISION 1 1/27/15
5
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY
CLOCK GENERATOR
More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

8735BMI-21LF Related Products

8735BMI-21LF 8735BKI-21LFT
Description SOIC-20, Tube VFQFPN-32, Reel
Brand Name Integrated Device Technology Integrated Device Technology
Is it lead-free? Lead free Lead free
Is it Rohs certified? conform to conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code SOIC VFQFPN
package instruction SOIC-20 VFQFN-32
Contacts 20 32
Manufacturer packaging code PSG20 NLG32P1
Reach Compliance Code compli compliant
ECCN code EAR99 EAR99
series 8735 8735
Input adjustment DIFFERENTIAL MUX DIFFERENTIAL MUX
JESD-30 code R-PDSO-G20 S-XQCC-N32
JESD-609 code e3 e3
length 12.8 mm 5 mm
Logic integrated circuit type PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER
Humidity sensitivity level 1 3
Number of functions 1 1
Number of terminals 20 32
Actual output times 4 4
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Package body material PLASTIC/EPOXY UNSPECIFIED
encapsulated code SOP HVQCCN
Package shape RECTANGULAR SQUARE
Package form SMALL OUTLINE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius) 260 260
propagation delay (tpd) 4.9 ns 4.9 ns
Same Edge Skew-Max（tskwd） 0.035 ns 0.035 ns
Maximum seat height 2.65 mm 1 mm
Maximum supply voltage (Vsup) 3.465 V 3.465 V
Minimum supply voltage (Vsup) 3.135 V 3.135 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V
surface mount YES YES
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface MATTE TIN Matte Tin (Sn)
Terminal form GULL WING NO LEAD
Terminal pitch 1.27 mm 0.5 mm
Terminal location DUAL QUAD
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED
width 7.5 mm 5 mm
minfmax 700 MHz 700 MHz

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