Low Phase Noise, Dual 1-to-4, 3.3V, 2.5V
LVPECL Output Fanout Buffer
8SLVP2104
Datasheet
Description
The 8SLVP2104I is a high-performance differential dual LVPECL
fanout buffer. The device is designed for the fanout of high-frequency,
very low additive phase-noise clock and data signals.
The 8SLVP2104I is characterized to operate from a 3.3V or 2.5V
power supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8SLVP2104I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. Two selectable differential inputs and four low skew
outputs are available. The integrated bias voltage reference enable
easy interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Two 1:4, low skew, low additive jitter LVPECL output pairs
Two differential clock input pairs
Differential pairs can accept the following differential input
levels: LVDS, LVPECL, CML
Maximum input clock frequency: 2GHz
Output skew: 8ps (typical)
Propagation delay: 270ps (maximum)
Low additive phase jitter, RMS: 47fs (maximum)
Full 3.3V and 2.5V supply voltage
Maximum device current consumption (I
EE
): 93mA (maximum)
Available in lead-free (RoHS 6), 28-Lead VFQFN package
-40°C to 85°C ambient operating temperature
Supports case temperature
105°C operations
Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also
accept single-ended LVCMOS levels. See Applications section
Wiring the Differential Input Levels to Accept Single-ended Levels
(Figure 1A and Figure 1B).
Block Diagram
QA0
nQA0
V
CC
Pin Assignments
nQA1
nQA3
nQA2
QA3
QA2
QA1
21 20 19 18 17 16 15
V
CC
PCLKA
nPCLKA
QA1
nQA1
QA2
nQA2
QA3
nQA3
QB0
nQB0
QB1
nQB1
QB2
nQB2
V
CC
22
23
24
25
26
27
28
1
V
EE
2
QB3
3
nQB3
4
nc
5
PCLKB
6
nPCLKB
7
V
REFB
14
13
12
11
10
9
8
V
EE
nQA0
QA0
V
REFA
nPCLKA
PCLKA
V
CC
V
REFA
Voltage
Reference
QB0
nQB0
V
CC
PCLKB
nPCLKB
QB1
nQB1
QB2
nQB2
QB3
nQB3
8SLVP2104I
28-VFQFN
5mm x 5mm x 0.75mm package body
NB Package
Top View
V
REFB
Voltage
Reference
©2019 Integrated Device Technology, Inc.
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January 15, 2019
8SLVP2104 Datasheet
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1, 14
2, 3
4
5
6
7
8, 15, 28
9
10
11
12, 13
16, 17
18, 19
20, 21
22, 23
24, 25
26, 27
Name
V
EE
QB3, nQB3
nc
PCLKB
nPCLKB
V
REFB
V
CC
PCLKA
nPCLKA
V
REFA
QA0, nQA0
QA1, nQA1
QA2, nQA2
QA3, nQA3
QB0, nQB0
QB1, nQB1
QB2, nQB2
Power
Output
Unused
Input
Input
Output
Power
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Type
Description
Negative supply pins.
Differential output pair B3. LVPECL interface levels.
Do not connect.
Non-inverting differential LVPECL clock/data input.
Inverting differential LVPECL clock/data input. V
CC
/2 default when left
floating.
Bias voltage reference for the PCLKB, nPCLKB input pair.
Power supply pins.
Non-inverting differential LVPECL clock/data input.
Inverting differential LVPECL clock/data input. V
CC
/2 default when left
floating.
Bias voltage reference for the PCLKA, nPCLKA input pair.
Differential output pair A0. LVPECL interface levels.
Differential output pair A1. LVPECL interface levels.
Differential output pair A2. LVPECL interface levels.
Differential output pair A3. LVPECL interface levels.
Differential output pair B0. LVPECL interface levels.
Differential output pair B1. LVPECL interface levels.
Differential output pair B2. LVPECL interface levels.
NOTE:
Pulldown
and
Pullup
refers to an internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
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8SLVP2104 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC Characteristics or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Maximum Junction Temperature, T
J,MAX
Storage Temperature, T
STG
Input Sink/Source, I
REF
ESD - Human Body Model, NOTE 1
ESD - Charged Device Model, NOTE 1
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
150°C
-65°C to 150°C
±2mA
2000V
1500V
NOTE 1: According to JEDEC/JESD 22-A114/22-C101. ESD ratings are target specifications.
Recommended Operating Conditions
Symbol
T
A
T
J
Parameter
Ambient air temperature
Junction temperature
Minimum
-40
Typical
Maximum
85
125
Units
C
C
NOTE 1: It is the user’s responsibility to ensure that device junction temperature remains below the maximum allowed.
NOTE 2: All conditions in the table must be met to guarantee device functionality.
NOTE 3: The device is verified to the maximum operating junction temperature through simulation.
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
I
CC
Parameter
Power Supply Voltage
Power Supply Current
Power Supply Current
QA[0:3] and QB[0:3]
terminated 50 to V
CC
– 2V
Test Conditions
Minimum
3.135
Typical
3.3V
Maximum
3.465
93
384
Units
V
mA
mA
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8SLVP2104 Datasheet
Table 3B. Power Supply DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
V
CC
I
EE
I
CC
Power Supply Voltage
Power Supply Current
Power Supply Current
QA[0:3] and QB[0:3]
terminated 50 to V
CC
– 2V
2.375
2.5V
2.625
83
379
V
mA
mA
Table 3C. LVPECL DC Characteristics, V
CC
= 3.3V ± 5%,
V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
Input
High
Current
Input
Low
Current
PCLKA, nPCLKA;
PCLKB, nPCLKB
PCLKA, PCLKB
nPCLKA, nPCLKB
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
I
REF
= 2mA
-10
-150
V
CC
– 1.6
V
CC
– 1.1
V
CC
– 2.0
V
CC
– 1.3
V
CC
– 0.9
V
CC
– 1.5
V
CC
– 1.1
V
CC
– 0.8
V
CC
– 1.4
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
I
IL
V
REFA,
V
REFB
V
OH
V
OL
Reference Voltage for Input Bias
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
NOTE: Input and output parameters vary 1:1 with V
CC
.
NOTE 1: Outputs terminated with 50 to V
CC
– 2V.
Table 3D. LVPECL DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
Input
High
Current
Input
Low
Current
PCLKA, nPCLKA;
PCLKB, nPCLKB
PCLKA, PCLKB
nPCLKA, nPCLKB
Test Conditions
V
CC
= V
IN
= 2.625V
V
CC
= 2.625V, V
IN
= 0V
V
CC
= 2.625V, V
IN
= 0V
I
REF
= 2mA
-10
-150
V
CC
– 1.6
V
CC
– 1.1
V
CC
– 2.0
V
CC
– 1.3
V
CC
– 0.9
V
CC
– 1.5
V
CC
– 1.1
V
CC
– 0.8
V
CC
– 1.4
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
I
IL
V
REFA,
V
REFB
V
OH
V
OL
Reference Voltage for Input Bias
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
NOTE: Input and output parameters vary 1:1 with V
CC
.
NOTE 1: Outputs terminated with 50 to V
CC
– 2V.
©2019 Integrated Device Technology, Inc.
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January 15, 2019
8SLVP2104 Datasheet
AC Electrical Characteristics
Table 4A. AC Electrical Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
REF
Parameter
Input
Frequency
PCLKA,
nPCLKA;
PCLKB,
nPCLKB
PCLKA,
nPCLKA;
PCLKB,
nPCLKB
PCLKA, nPCLKA to any
QAx, nQAx or PCLKB, nPCLKB to any
QBx, nQBx for V
PP
= 0.1V or 0.3V
f
REF
= 122.88MHz
Any Output
Within QAx, QBx
f
REF
= 100MHz
1.5
Test Conditions
Minimum
Typical
Maximum
2
Units
GHz
V/t
Input
Edge Rate
V/ns
t
PD
Propagation Delay; NOTE
1
50
165
78
8
7
7
100
270
ps
dB
Channel_
ISOL
Channel Isolation
tsk(o)
tsk(b)
tsk(p)
tsk(pp)
Output Skew; NOTE 2, 3
Bank Skew; NOTE 3, 4
Pulse Skew
Part-to-Part Skew; NOTE
3, 5
25
20
27
200
ps
ps
ps
ps
t
JIT, SP
Spurious Suppression,
Coupling from QA3 to QB0
f
QB0
= 500MHz, V
PP(PCLKB)
= 0.15V,
V
CMR(PCLKB)
= 1V and
f
QA3
= 62.5MHz, V
PP(PCLKA)
= 1V,
V
CMR(PCLKA)
= 1V
f
QB0
= 500MHz, V
PP(PCLKB)
= 0.15V,
V
CMR(PCLKB)
= 1V and
f
QA3
= 15.625MHz, V
PP(PCLKA)
= 1V,
V
CMR(PCLKA)
= 1V
20% to 80%
f
REF
< 1.5 GHz
f
REF
> 1.5 GHz
40
0.1
0.2
1.0
V
CC
= 3.3V, f
REF
2GHz
V
CC
= 2.5V, f
REF
2GHz
V
CC
= 3.3V, f
REF
2GHz
V
CC
= 2.5V, f
REF
2GHz
0.4
0.35
0.8
0.7
-66
dB
-77
100
150
1.5
1.5
V
CC
– 0.6
0.6
0.55
1.2
1.1
1.0
1.0
2.0
2.0
dB
ps
V
V
V
V
V
V
V
t
R
/ t
F
V
PP
V
CMR
V
O
(pp)
V
DIFF_OUT
Output Rise/ Fall Time
Peak-to-Peak Input
Voltage; NOTE 6, 8
Common Mode Input
Voltage; NOTE 6, 7, 8
Output Voltage Swing,
Peak-to-Peak
Differential Output Voltage
Swing, (Peak-to-Peak)
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crosspoint.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential
crosspoints.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew within a bank with equal load conditions. Measured at the differential crosspoints.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoints.
NOTE 6: V
IL
should not be less than -0.3V. V
IH
should not be higher than V
CC
.
NOTE 7: Common mode input voltage is defined as the crosspoint.
NOTE 8: For single-ended LVCMOS input applications, please refer to the Applications Information, Wiring the Differential Input to accept
single-ended levels, Figures 1A and 1B.
©2019 Integrated Device Technology, Inc.
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January 15, 2019
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