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8SLVP2106ANLGI8

Description
VFQFPN-40, Reel
Categorylogic    logic   
File Size992KB，25 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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8SLVP2106ANLGI8 Overview

VFQFPN-40, Reel

8SLVP2106ANLGI8 Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeVFQFPN
package instructionVFQFN-40
Contacts40
Manufacturer packaging codeNLG40P1
Reach Compliance Codecompli
ECCN codeEAR99
Samacsys DescriptiVFQFP-N 6.0 X 6.0 X 0.9 MM - NO LEAD
Other featuresALSO OPERATES AT 3.3 V SUPPLY
series8SLVP
Input adjustmentDIFFERENTIAL
JESD-30 codeS-XQCC-N40
JESD-609 codee3
length6 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Humidity sensitivity level3
Number of functions2
Number of inverted outputs
Number of terminals40
Actual output times12
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialUNSPECIFIED
encapsulated codeVQCCN
Encapsulate equivalent codeLCC40,.24SQ,20
Package shapeSQUARE
Package formCHIP CARRIER, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)260
power supply2.5/3.3 V
Prop。Delay @ Nom-Su0.34 ns
propagation delay (tpd)0.34 ns
Certification statusNot Qualified
Same Edge Skew-Max（tskwd）0.06 ns
Maximum seat height1 mm
Maximum supply voltage (Vsup)2.625 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width6 mm

8SLVP2106ANLGI8 Preview

Low Phase Noise, Dual 1-to-6, 3.3V, 2.5V
LVPECL Output Fanout Buffer
8SLVP2106
DATA SHEET
General Description
The 8SLVP2106 is a high-performance differential dual 1:6 LVPECL
fanout buffer. The device is designed for the fanout of high-frequency,
very low additive phase-noise clock and data signals. The
8SLVP2106 is characterized to operate from a 3.3V or 2.5V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8SLVP2106 ideal for those clock distribution
applications demanding well-defined performance and repeatability.
Two independent buffers with six low skew outputs each are
available. The integrated bias voltage references enable easy
interfacing of single-ended signals to the device inputs. The device is
optimized for low power consumption and low additive phase noise.
Features
•
•
•
•
Two 1:6, low skew, low additive jitter LVPECL fanout buffers
Two differential clock inputs
Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can
accept the following differential input levels: LVDS, LVPECL, CML
Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also
accept single-ended LVCMOS levels. See Applications section
Wiring the Differential Input Levels to Accept Single-ended Levels
(Figure 1A and Figure 1B).
Maximum input clock frequency: 2GHz
Output bank skew: 15ps (typical)
Propagation delay: 340ps (maximum)
Low additive phase jitter, RMS: 54fs (maximum)
f
REF
= 156.25MHz, V
PP
= 1V, 12kHz - 20MHz: V
CC
= 3.3V)
Full 3.3V and 2.5V supply voltage modes
Maximum device current consumption (I
EE
): 114mA
Available in Lead-free (RoHS 6), 40-Lead VFQFN package
-40°C to 85°C ambient operating temperature
Supports case temperature
105°C operations
•
•
•
•
•
•
•
•
•
Block Diagram
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
QA4
nQA4
V
REFA
Voltage
Reference
QA5
nQA5
QB0
nQB0
QB1
nQB1
V
CC
V
CC
PCLKA
nPCLKA
Pin Assignment
nQB1
nQB0
nQA5
nQA4
QB1
QB0
QA5
QA4
22
V
EE
30
29
28
27
26
25
24
23
21
20
V
CC
19
nQA3
18
QA3
V
CC
31
QB2
32
nQB2
33
QB3
34
nQB3
35
QB4
36
PCLKB
nPCLKB
QB2
nQB2
QB3
nQB3
QB4
nQB4
nQB4
37
QB5
38
nQB5
39
V
CC
40
8SLVP2106i
40-lead VFQFN
6mm x 6mm x 0.925mm package body
NL Package
Top View
V
EE
17
nQA2
16
QA2
15
nQA1
14
QA1
13
nQA0
12
QA0
11
V
CC
10
V
REFB
Voltage
Reference
nPCLKB
nPCLKA
PCLKB
VREFB
PCLKA
VREFA
V
CC
V
CC
nc
8SLVP2106 REVISION B 6/9/15
1
©2015 Integrated Device Technology, Inc.
nc
QB5
nQB5
1
2
3
4
5
6
7
8
9
8SLVP2106 DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1, 10
2
3
4
5, 6, 11, 20,
31, 40
7
8
9
12, 13
14, 15
16, 17
18, 19
21, 30
22, 23
24, 25
26, 27
28, 29
32, 33
34, 35
36, 37
38, 39
Name
nc
PCLKB
nPCLKB
V
REFB
V
CC
V
REFA
nPCLKA
PCLKA
QA0, nQA0
QA1, nQA1
QA2, nQA2
QA3, nQA3
V
EE
QA4, nQA4
QA5, nQA5
QB0, nQB0
QB1, nQB1
QB2, nQB2
QB3, nQB3
QB4, nQB4
QB5, nQB5
Unused
Input
Input
Output
Power
Output
Input
Input
Output
Output
Output
Output
Power
Output
Output
Output
Output
Output
Output
Output
Output
Pulldown/
Pullup
Pulldown
Pulldown
Pulldown/
Pullup
Type
Description
Do not connect.
Non-inverting LVPECL differential clock/data input.
Inverting LVPECL differential clock input.
Bias voltage reference for the PCLKB, nPCLKB input pair.
Power supply pins.
Bias voltage reference for the PCLKA, nPCLKA input pair.
Inverting LVPECL differential clock input.
Non-inverting LVPECL differential clock/data input.
Differential output pair A0. LVPECL interface levels.
Differential output pair A1. LVPECL interface levels.
Differential output pair A2. LVPECL interface levels.
Differential output pair A3. LVPECL interface levels.
Negative supply pins.
Differential output pair A4. LVPECL interface levels.
Differential output pair A5. LVPECL interface levels.
Differential output pair B0. LVPECL interface levels.
Differential output pair B1. LVPECL interface levels.
Differential output pair B2. LVPECL interface levels.
Differential output pair B3. LVPECL interface levels.
Differential output pair B4. LVPECL interface levels.
Differential output pair B5. LVPECL interface levels.
NOTE:
Pulldown
and
Pullup
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
LOW PHASE NOISE, DUAL 1-TO-6, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
2
REVISION B 6/9/15
8SLVP2106 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC Characteristics or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Input Sink/Source, I
REF
Maximum Junction Temperature, T
J,MAX
Storage Temperature, T
STG
ESD - Human Body Model (NOTE 1)
ESD - Charged Device Model (NOTE 1)
NOTE 1: According to JEDEC/JESD 22-A114/22-C101.
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
±2mA
125
C
-65C to 150C
2000V
1500V
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
I
CC
Parameter
Power Supply Voltage
Power Supply Current
Power Supply Current
QA[0:5] and QB[0:5] terminated
50 to V
CC
– 2V
Test Conditions
Minimum
3.135
Typical
3.3V
94
503
Maximum
3.465
114
569
Units
V
mA
mA
Table 3B. Power Supply DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
I
CC
Parameter
Power Supply Voltage
Power Supply Current
Power Supply Current
QA[0:5] and QB[0:5] terminated
50 to V
CC
– 2V
Test Conditions
Minimum
2.375
Typical
2.5V
89
502
Maximum
2.625
103
569
Units
V
mA
mA
REVISION B 6/9/15
3
LOW PHASE NOISE, DUAL 1-TO-6, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
8SLVP2106 DATA SHEET
Table 3C. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
REFx
V
OH
V
OL
Parameter
Input High
Current
Input Low
Current
PCLKA, nPCLKA
PCLKB, nPCLKB
PCLKA, PCLKB
nPCLKA, nPCLKB
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
I
REF
= 2mA
-10
-150
V
CC
– 1.82
V
CC
– 1.05
V
CC
– 1.50
V
CC
– 1.48
V
CC
– 0.89
V
CC
– 1.38
V
CC
– 1.27
V
CC
– 0.72
V
CC
– 1.26
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
Reference Voltage for Input
Bias
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
NOTE: V
REFx
denotes V
REFA
and V
REFB.
NOTE 1: Outputs terminated with 50 to V
CC
– 2V.
Table 3D. LVPECL DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
REFx
V
OH
V
OL
Parameter
Input High Current
PCLKA, nPCLKA
PCLKB, nPCLKB
PCLKA, PCLKB
Input Low Current
nPCLKA, nPCLKB
Reference Voltage for Input Bias;
NOTE 2
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Test Conditions
V
CC
= V
IN
= 2.625V
V
CC
= 2.625V, V
IN
= 0V
V
CC
= 2.625V, V
IN
= 0V
I
REF
= 2mA
-10
-150
V
CC
– 1.81
V
CC
– 1.05
V
CC
– 1.48
V
CC
– 1.47
V
CC
– 0.89
V
CC
– 1.36
V
CC
– 1.27
V
CC
– 0.73
V
CC
– 1.23
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
NOTE: V
REFx
denotes V
REFA
and V
REFB.
NOTE 1: Outputs terminated with 50 to V
CC
– 2V.
NOTE 2: For V
CC
< 3V, the use of an alternate bias voltage source is recommended.
LOW PHASE NOISE, DUAL 1-TO-6, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
4
REVISION B 6/9/15
8SLVP2106 DATA SHEET
AC Electrical Characteristics
Table 4A. AC Electrical Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
REF
V/t
t
PD
tsk(o)
tsk(b)
tsk(p)
tsk(pp)
Parameter
Input Frequency
Input Edge Rate
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 3
Output Bank Skew; NOTE 3,
4
Pulse Skew
Part-to-Part Skew; NOTE 3, 5
f
QB0
= 500MHz, V
PP(PCLKB)
= 0.15V,
V
CMR(PCLKB)
= 1V;
f
QA5
= 62.5MHz, V
PP(PCLKA)
= 1V,
V
CMR(PCLKA)
= 1V
f
QB0
= 500MHz, V
PP(PCLKB)
= 0.15V,
V
CMR(PCLKB)
= 1V;
f
QA5
= 15.625MHz, V
PP(PCLKA)
= 1V,
V
CMR(PCLKA)
= 1V
20% to 80%
f
REF
1.5GHz
f
REF
1.5GHz
60
0.1
0.2
1.0
f
REF

2GHz, V
CC
= 2.5V ± 5%
f
REF

2GHz, V
CC
= 3.3V ± 5%
f
REF

2GHz, V
CC
= 2.5V ± 5%
f
REF

2GHz, V
CC
= 3.3V ± 5%
0.31
0.33
0.62
0.66
0.46
0.49
0.92
0.98
f
REF
= 100MHz
Test Conditions
PCLKA, nPCLKA and PCLKB, nPCLKB
PCLKA, nPCLKA and PCLKB, nPCLKB
PCLKA, nPCLKA to any QAx, nQAx or
PCLKB, nPCLKB to any QBx, nQBx
for V
PP
= 0.1V or 0.3V
1.5
130
235
26
15
6
66
340
60
42
26
144
Minimum
Typical
Maximum
2
Units
GHz
V/ns
ps
ps
ps
ps
ps
-52
dB
t
JIT, SP
Spurious Suppression,
Coupling from QA5 to QB0
-63
dB
t
R
/ t
F
V
PP
V
CMR
V
O
(pp)
Output Rise/ Fall Time;
NOTE 6
Differential Input Voltage;
NOTE 7, 8
Common Mode Input
Voltage; NOTE 7, 8, 9
Output Voltage Swing,
Peak-to-Peak
100
170
1.5
1.5
V
CC
– 0.3
0.62
0.66
1.24
1.32
ps
V
V
V
V
V
V
V
V
DIFF_OU
Differential Output Voltage
Swing, Peak-to-Peak
T
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crosspoint to the differential output crosspoint.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoints.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. Measured at the differential
crosspoints.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoints.
NOTE 6: Characterized with input signal meeting the input edge rate minimum specification.
NOTE 7: For single-ended LVCMOS input applications, please refer to the Applications Information,
Wiring the Differential Input to Accept
Single-ended Levels,
Figures 1A and 1B.
NOTE 8: V
IL
should not be less than -0.3V. V
IH
should not be higher than V
CC
.
NOTE 9: Common mode input voltage is defined at the crosspoint.
REVISION B 6/9/15
5
LOW PHASE NOISE, DUAL 1-TO-6, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
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8SLVP2106ANLGI8 Related Products

8SLVP2106ANLGI8 8SLVP2106ANLGI
Description VFQFPN-40, Reel VFQFPN-40, Tray
Brand Name Integrated Device Technology Integrated Device Technology
Is it lead-free? Lead free Lead free
Is it Rohs certified? conform to conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code VFQFPN VFQFPN
package instruction VFQFN-40 VFQFN-40
Contacts 40 40
Manufacturer packaging code NLG40P1 NLG40P1
Reach Compliance Code compli compliant
ECCN code EAR99 EAR99
Other features ALSO OPERATES AT 3.3 V SUPPLY ALSO OPERATES AT 3.3 V SUPPLY
series 8SLVP 8SLVP
Input adjustment DIFFERENTIAL DIFFERENTIAL
JESD-30 code S-XQCC-N40 S-XQCC-N40
JESD-609 code e3 e3
length 6 mm 6 mm
Logic integrated circuit type LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER
Humidity sensitivity level 3 3
Number of functions 2 2
Number of terminals 40 40
Actual output times 12 12
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Package body material UNSPECIFIED UNSPECIFIED
encapsulated code VQCCN VQCCN
Encapsulate equivalent code LCC40,.24SQ,20 LCC40,.24SQ,20
Package shape SQUARE SQUARE
Package form CHIP CARRIER, VERY THIN PROFILE CHIP CARRIER, VERY THIN PROFILE
Peak Reflow Temperature (Celsius) 260 260
power supply 2.5/3.3 V 2.5/3.3 V
propagation delay (tpd) 0.34 ns 0.34 ns
Certification status Not Qualified Not Qualified
Same Edge Skew-Max（tskwd） 0.06 ns 0.06 ns
Maximum seat height 1 mm 1 mm
Maximum supply voltage (Vsup) 2.625 V 2.625 V
Minimum supply voltage (Vsup) 2.375 V 2.375 V
Nominal supply voltage (Vsup) 2.5 V 2.5 V
surface mount YES YES
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface Matte Tin (Sn) Matte Tin (Sn)
Terminal form NO LEAD NO LEAD
Terminal pitch 0.5 mm 0.5 mm
Terminal location QUAD QUAD
Maximum time at peak reflow temperature 30 30
width 6 mm 6 mm

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