IDT70V24S15G datasheet, PDF - EEWORLD Datasheet

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IDT70V24S15G: DescriptionDual-Port SRAM, 4KX16, 15ns, CMOS, CPGA84, 1.120 X 1.120 INCH, 0.160 INCH HEIGHT, CERAMIC, PGA-84; Categorystorage storage; File Size180KB，22 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT70V24S15G Overview

Dual-Port SRAM, 4KX16, 15ns, CMOS, CPGA84, 1.120 X 1.120 INCH, 0.160 INCH HEIGHT, CERAMIC, PGA-84

IDT70V24S15G Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	PGA
package instruction	PGA, PGA84M,11X11
Contacts	84
Reach Compliance Code	_compli
ECCN code	EAR99
Maximum access time	15 ns
Other features	INTERRUPT FLAG; SEMAPHORE; AUTOMATIC POWER-DOWN
I/O type	COMMON
JESD-30 code	S-CPGA-P84
JESD-609 code	e0
length	27.94 mm
memory density	65536 bi
Memory IC Type	DUAL-PORT SRAM
memory width	16
Number of functions	1
Number of ports	2
Number of terminals	84
word count	4096 words
character code	4000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4KX16
Output characteristics	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Encapsulate equivalent code	PGA84M,11X11
Package shape	SQUARE
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	5.207 mm
Maximum standby current	0.005 A
Minimum standby current	3 V
Maximum slew rate	0.215 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	30
width	27.94 mm

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HIGH-SPEED 3.3V

4K x 16 DUAL-PORT

STATIC RAM

Features

IDT70V24S/L

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

– Commercial: 15/20/25/35/55ns (max.)

– Industrial: 20/25/35/55ns (max.)

Low-power operation

– IDT70V24S

Active: 400mW (typ.)

Standby: 3.3mW (typ.)

– IDT70V24L

Active: 380mW (typ.)

Standby: 660

W (typ.)

Separate upper-byte and lower-byte control for multiplexed

bus compatibility

IDT70V24 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

M/S = V

for

BUSY

output flag on Master

M/S = V

for

BUSY

input on Slave

BUSY

and Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

LVTTL-compatible, single 3.3V (±0.3V) power supply

Available in 84-pin PGA, 84-pin PLCC and 100-pin TQFP

Industrial temperature range (-40°C to +85°C) is available

for selected speeds

Functional Block Diagram

I/O

-I/O

15L

I/O

Control

I/O

-I/O

I/O

Control

I/O

-I/O

15R

I/O

-I/O

BUSY

(1,2)

BUSY

(1,2)

Address

Decoder

11L

MEMORY

ARRAY

Address

Decoder

11R

SEM

(2)

INT

NOTES:

1. (MASTER):

BUSY

is output; (SLAVE):

BUSY

is input.

BUSY

outputs and

INT

outputs are non-tri-stated push-pull.

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

SEM

INT

(2)

2911 drw 01

MARCH 2000

DSC-2911/8

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