2.5V MULTI-QUEUE FIFO (32 QUEUES)
36 BIT WIDE CONFIGURATION
1,179,648 bits
2,359,296 bits
ADVANCE INFORMATION
IDT72T51546
IDT72T51556
FEATURES:
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Choose from among the following memory density options:
IDT72T51546
Total Available Memory = 1,179,648 bits
IDT72T51556
Total Available Memory = 2,359,296 bits
Configurable from 1 to 32 Queues
Queues may be configured at master reset from the pool of
Total Available Memory in blocks of 256 x 36
Independent Read and Write access per queue
User programmable via serial port
User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL
Default Multi-Queue device configurations
– IDT72T51546 : 1,024 x 36 x 32Q
– IDT72T51556 : 2,048 x 36 x 32Q
100% Bus Utilization, Read and Write on every clock cycle
200 MHz High speed operation (5ns cycle time)
3.6ns access time
Echo Read Enable & Echo Read Clock Outputs
Individual, Active queue flags (OV,
FF, PAE, PAF, PR)
8 bit parallel flag status on both read and write ports
Shows
PAE
and
PAF
status of 8 Queues
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Direct or polled operation of flag status bus
Global Bus Matching - (All Queues have same Input Bus Width
and Output Bus Width)
User Selectable Bus Matching Options:
– x36in to x36out
– x18in to x36out
– x9in to x36out
– x36in to x18out
– x36in to x9out
FWFT mode of operation on read port
Packet Ready mode of operation
Partial Reset, clears data in single Queue
Expansion of up to 8 Multi-Queue devices in parallel is available
Power Down Input provides additional power savings in HSTL
and eHSTL modes.
JTAG Functionality (Boundary Scan)
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
HIGH Performance submicron CMOS technology
Industrial temperature range (-40°C to +85°C) is available
DATA PATH FLOW DIAGRAM
MULTI-QUEUE FIFO
WADEN
FSTR
WRADD
8
Q0
READ CONTROL
8
RADEN
ESTR
RDADD
REN
RCLK
WRITE CONTROL
Q1
WEN
WCLK
EREN
ERCLK
OE
Q2
Din
Qout
x36
DATA IN
FF
PAF
PAFn
x36
DATA OUT
READ FLAGS
OV
PR
PAE
PAEn
8
WRITE FLAGS
Qmax
8
PRn
5998 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©2001
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
OCTOBER 2, 2001
DSC-5998/-
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FIFO (32 QUEUES)
36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION:
The IDT72T51546/72T51556 Multi-Queue FIFO device is a single chip
within which anywhere between 1 and 32 discrete FIFO queues can be setup.
All queues within the device have a common data input bus, (write port) and
a common data output bus, (read port). Data written into the write port is directed
to a respective queue via an internal de-multiplex operation, addressed by
the user. Data read from the read port is accessed from a respective queue
via an internal multiplex operation, addressed by the user. Data writes and
reads can be performed at high speeds up to 200MHz, with access times of
3.6ns. Data write and read operations are totally independent of each other,
a queue maybe selected on the write port and a different queue on the read
port or both ports may select the same queue simultaneously.
The device provides Full flag and Output Valid flag status for the queue
selected for write and read operations respectively. Also a Programmable
Almost Full and Programmable Almost Empty flag for each queue is provided.
Two 8 bit programmable flag busses are available, providing status of queues
not selected for write or read operations. When 8 or less queues are configured
in the device these flag busses provide an individual flag per queue, when
more than 8 queues are used, either a Polled or Direct mode of bus operation
provides the flag busses with all queues status.
Bus Matching is available on this device, either port can be 9 bits, 18 bits
or 36 bits wide provided that at least one port is 36 bits wide. When Bus Matching
is used the device ensures the logical transfer of data throughput in a Little
Endian manner.
A packet ready mode of operation is also provided when the device is
configured for 36 bit input and 36 bit output port sizes. The Packet Ready mode
provides the user with a flag output indicating when at least one (or more)
packets of data within a queue is available for reading. The Packet Ready
provides the user with a means by which to mark the start and end of packets
of data being passed through the FIFO queues. The Multi-Queue device then
provides the user with an internally generated packet ready status per queue.
The user has full flexibility configuring queues within the device, being able
to program the total number of queues between 1 and 32, the individual queue
depths being independent of each other. The programmable flag positions are
also user programmable. All programming is done via a dedicated serial port.
If the user does not wish to program the Multi-Queue device, a default option is
available that configures the device in a predetermined manner.
Both Master Reset and Partial Reset pins are provided on this device. A Master
Reset latches in all configuration setup pins and must be performed before
programming of the device can take place. A Partial Reset will reset the read and
write pointers of an individual FIFO queue, provided that the queue is selected
on both the write port and read port at the time of partial reset.
Echo Read Enable,
EREN
and Echo Read Clock, ERCLK outputs are
provided. These are outputs from the read port of the FIFO that are required for
high speed data communication, to provide tighter synchronization between the
data being transmitted from the Qn outputs and the data being received by the
input device. Data read from the read port is available on the output bus with
respect to
EREN
and ERCLK, this is very useful when data is being read at high
speed.
The Multi-Queue FIFO has the capability of operating its IO in either 2.5V
LVTTL, 1.5V HSTL or 1.8V eHSTL mode. The type of IO is selected via the
IOSEL input. The core supply voltage (V
CC
) to the Multi-Queue is always 2.5V,
however the output levels can be set independently via a separate supply, V
DDQ
.
The devices also provide additional power savings via a Power Down Input.
This input disables the write port data inputs when no write operations are
required.
A JTAG test port is provided, here the Multi-Queue FIFO has a fully functional
Boundary Scan feature, compliant with IEEE 1449.1 Standard Test Access Port
and Boundary Scan Architecture.
See Figure 1,
Multi-Queue FIFO Block Diagram
for an outline of the functional
blocks within the device.
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IDT72T51546/72T51556 2.5V, MULTI-QUEUE FIFO (32 QUEUES)
36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DETAILED DESCRIPTION
MULTI-QUEUE STRUCTURE
The IDT Multi-Queue FIFO has a single data input port and single data output
port with up to 32 FIFO queues in parallel buffering between the two ports. The
user can setup between 1 and 32 FIFO Queues within the device. These
queues can be configured to utilize the total available memory, providing the user
with full flexibility and ability to configure the queues to be various depths,
independent of one another.
MEMORY ORGANIZATION/ ALLOCATION
The memory is organized into what is known as “blocks”, each block being
256 x36 bits. When the user is configuring the number of queues and individual
queue sizes the user must allocate the memory to respective queues, in units
of blocks, that is, a single queue can be made up from 0 to m blocks, where m
is the total number of blocks available within a device. Also the total size of any
given queue must be in increments of 256 x36. For the IDT72T51546 and
IDT72T51556 the Total Available Memory is 128 and 256 blocks respectively
(a block being 256 x36). Queues can be built from these blocks to make any
size queue desired and any number of queues desired.
BUS WIDTHS
The input port is common to all FIFO queues within the device, as is the output
port. The device provides the user with Bus Matching options such that the input
port and output port can be either x9, x18 or x36 bits wide provided that at least
one of the ports is x36 bits wide, the read and write port widths being set
independently of one another. Because the ports are common to all queues the
width of the queues is not individually set, so that the input width of all queues
are equal and the output width of all queues are equal.
WRITING TO & READING FROM THE MULTI-QUEUE
Data being written into the device via the input port is directed to a discrete
FIFO queue via the write queue select address inputs. Conversely, data being
read from the device read port is read from a queue selected via the read queue
select address inputs. Data can be simultaneously written into and read from the
same FIFO queue or different FIFO queues. Once a queue is selected for data
writes or reads, the writing and reading operation is performed in the same
manner as a conventional IDT synchronous FIFO’s, utilizing clocks and
enables, there is a single clock and enable per port. When a specific queue is
addressed on the write port, data placed on the data inputs is written to that queue
sequentially based on the rising edge of a write clock provided setup and hold
times are met. Conversely, data is read on to the output port after an access time
from a rising edge on a read clock.
The operation of the write port is comparable to the function of a conventional
FIFO operating in standard IDT mode. Write operations can be performed on
the write port provided that the queue currently selected is not full, a full flag output
provides status of the selected queue. The operation of the read port is
comparable to the function of a conventional FIFO operating in FWFT mode.
When a FIFO queue is selected on the output port, the next word in that queue
will automatically fall through to the output register. All subsequent words from
that queue require an enabled read cycle. Data cannot be read from a selected
queue if that queue is empty, the read port provides an Output Valid flag indicating
when data read out is valid. If the user switches to a queue that is empty, the
last word from the previous queue will remain on the output register.
As mentioned, the write port has a full flag, providing full status of the selected
queue. Along with the full flag a dedicated almost full flag is provided, this almost
full flag is similar to the almost full flag of a conventional IDT FIFO. The device
provides a user programmable almost full flag for all 32 FIFO queues and when
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a respective queue is selected on the write port, the almost full flag provides status
for that queue. Conversely, the read port has an output valid flag, providing
status of the data being read from the queue selected on the read port. As well
as the output valid flag the device provides a dedicated almost empty flag. This
almost empty flag is similar to the almost empty flag of a conventional IDT FIFO.
The device provides a user programmable almost empty flag for all 32 FIFO
queues and when a respective queue is selected on the read port, the almost
empty flag provides status for that queue.
PROGRAMMABLE FLAG BUSSES
In addition to these dedicated flags, full & almost full on the write port and output
valid & almost empty on the read port, there are two flag status busses. An almost
full flag status bus is provided, this bus is 8 bits wide. Also, an almost empty flag
status bus is provided, again this bus is 8 bits wide. The purpose of these flag
busses is to provide the user with a means by which to monitor the data levels
within FIFO queues that may not be selected on the write or read port. As
mentioned, the device provides almost full and almost empty registers (program-
mable by the user) for each of the 32 FIFO queues in the device.
In the IDT72T51546/72T51556 Multi-Queue FIFO device the user has the
option of utilizing anywhere between 1 and 32 FIFO queues, therefore the 8
bit flag status busses are multiplexed between the 32 queues, a flag bus can only
provide status for 8 of the 32 queues at any moment, this is referred to as a
“Quadrant”, such that when the bus is providing status of queues 1 through 8,
this is quadrant 1, when it is queues 9 through 16, this is quadrant 2 and so on
up to quadrant 4. If less than 32 queues are setup in the device, there are still
4 quadrants, such that in “Polled” mode of operation the flag bus will still cycle
through 4 quadrants. If for example only 22 queues are setup, quadrants 1 and
2 will reflect status of queues 1 through 8 and 9 through 16 respectively.
Quadrant 3 will reflect the status of queues 17 through 22 on the least significant
6 bits, the most significant 2 bits of the flag bus are don’t care and the 4th quadrant
outputs will be don’t care also.
The flag busses are available in two user selectable modes of operation,
“Polled” or “Direct”. When operating in polled mode a flag bus provides status
of each quadrant sequentially, that is, on each rising edge of a clock the flag bus
is updated to show the status of each quadrant in order. The rising edge of the
write clock will update the almost full bus and a rising edge on the read clock will
update the almost empty bus. The mode of operation is always the same for both
the almost full and almost empty flag busses. When operating in direct mode, the
quadrant on the flag bus is selected by the user. So the user can actually address
the quadrant to be placed on the flag status busses, these flag busses operate
independently of one another. Addressing of the almost full flag bus is done via
the write port and addressing of the almost empty flag bus is done via the read
port.
PACKET READY
The 36 bit Multi-Queue FIFO also offers a ”Packet Ready” mode of operation,
this is user selectable and requires that the device be configured with both write
and read ports as 36 bits wide. The packet mode of operation provides
monitoring of “user marked” locations, when the user is writing data into a FIFO
queue a word being written in can be marked as a “Start of Packet” or “End of
Packet”. Internally as words are being written into the device with markers
attached, the device monitors these markers and provides a packet ready status
flag, which indicates when at least one full packet is available in a queue. The
read port therefore includes an additional status flag, “Packet Ready”, this flag
providing packet ready status for the queue currently selected on the read port
for read operations, indicating when at least one (or more) packets of data are
available to be read. When in packet ready mode the almost empty flag status
bus no longer provides almost empty status for individual quadrants, but instead
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