Features
•
8-Bit Multiplexed Addresses/Outputs
•
Fast Read Access Time - 90 ns
•
Dual Voltage Range Operation
•
•
•
•
•
•
•
– Low-Voltage Power Supply Range, 3.0V to 3.6V, or
– Standard 5V
±
10% Supply Range
Low Power CMOS Operation
– 20
µ
A max. Standby for ALE = V
IH
and V
CC
= 3.6V
– 29 mW max. Active at 5 MHz for V
CC
= 3.6V
20-Lead TSSOP Package
High Reliability CMOS Technology
– 2,000V ESD Protection
– 200 mA Latchup Immunity
Rapid
™
Programming Algorithm - 50
µ
s/byte (typical)
CMOS and TTL Compatible Inputs and Outputs
– JEDEC Standard for LVTTL
Integrated Product Identification Code
Commercial and Industrial Temperature Range
Description
The AT27LV520 is a low-power, high-performance 524,288-bit one-time programma-
ble read only memory (OTP EPROM) organized 64K by 8 bits. It incorporates latches
for the 8 lower order address bits to multiplex with the 8 data bits. This minimizes sys-
tem chip count, reduces cost, and simplifies the design of multiplexed bus systems. It
requires only one power supply in the range of 3.0V to 3.6V for normal read mode
operation, making it ideal for fast, portable systems using battery power. Any byte can
be accessed in less than 90 ns.
The AT27LV520 is available in 173 mil, 20-pin TSSOP, 300 mil, 20-pin SOIC and 28-
pin TSOP, one-time programmable (OTP) plastic packages.
(continued)
512K (64K x 8)
Multiplexed
Addresses/
Outputs
Low Voltage
OTP EPROM
AT27LV520
Pin Configurations
Pin Name
A8 - A15
AD0 - AD7
OE /V
PP
ALE
Function
Addresses
Addresses/Outputs
Output Enable/V
PP
Address Latch Enable
TSOP Top View
A10
NC
NC
A12
A14
ALE
VCC
OE/VPP
A15
A13
A11
NC
NC
A9
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A8
NC
NC
AD1
AD3
AD5
AD7
GND
AD6
AD4
AD2
NC
NC
AD0
TSSOP Top View
A10
A12
A14
ALE
VCC
OE/VPP
A15
A13
A11
A9
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
A8
AD1
AD3
AD5
AD7
GND
AD6
AD4
AD2
AD0
SOIC Top View
OE/VPP
A15
A13
A11
A9
AD0
AD2
AD4
AD6
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
ALE
A14
A12
A10
A8
AD1
AD3
AD5
AD7
Rev. 0911B-B–01/98
1
Atmel’s innovative design techniques provide fast speeds
that rival 5V parts while keeping the low power consump-
tion of a 3.3V supply. At V
CC
= 3.0V, any byte can be
accessed in less than 90 ns. With a typical power dissipa-
tion of only 18 mW at 5 MHz and V
C C
= 3.3V, the
AT27LV520 consumes less than one fifth the power of a
standard 5V EPROM. Standby mode is acheived by assert-
ing ALE high. Standby mode supply current is typically less
than 1
µA
at 3.3V.
The AT27LV520 operating with V
CC
at 3.0V produces TTL
level outputs that are compatible with standard TTL logic
devices operating at V
CC
= 5.0V. The device is also capa-
ble of standard 5-volt operation making it ideally suited for
dual supply range systems or card products that are plug-
gable in both 3-volt and 5-volt hosts.
Atmel’s AT27LV520 has additional features to ensure high
quality and efficient production use. The Rapid
™
Program-
ming Algorithm reduces the time required to program the
part and guarantees reliable programming. Programing
time is typically only 50
µs/byte.
The Integrated Product
Identification Code electronically identifies the device and
manufacturer. This feature is used by industry standard
programming equipment to select the proper programming
algorithms and voltages. The AT27LV520 programs exactly
the same way as a standard 5V AT27C520 and uses the
same programming equipment.
System Considerations
Switching under active conditions may produce transient
voltage excursions. Unless accommodated by the system
design, these transients may exceed data sheet limits,
resulting in device non-conformance. At a minimum, a 0.1
µF
high frequency, low inherent inductance, ceramic
capacitor should be utilized for each device. This capacitor
should be connected between the V
CC
and Ground termi-
nals of the device, as close to the device as possible. Addi-
tionally, to stabilize the supply voltage level on printed cir-
cuit boards with large EPROM arrays, a 4.7
µF
bulk elec-
trolytic capacitor should be utilized, again connected
between the V
CC
and Ground terminals. This capacitor
should be positioned as close as possible to the point
where the power supply is connected to the array.
Block Diagram
V
CC
GND
OE/VPP
ALE
OE, ALE, AND
PROGRAM LOGIC
OUTPUT
BUFFERS
8
LATCHES
Y DECODER
Y-GATING
AD7 - AD0
A15 - A8
8
X DECODER
CELL MATRIX
IDENTIFICATION
2
AT27LV520
AT27LV520
Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground ........................................ -2.0V to +7.0V
(1)
Voltage on A9 with
Respect to Ground ..................................... -2.0V to +14.0V
(1)
Note:
V
PP
Supply Voltage with
Respect to Ground ...................................... -2.0V to +14.0V
(1)
1.
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Minimum voltage is -0.6V DC which may under-
shoot to -2.0V for pulses of less than 20 ns. Max-
imum output pin voltage is V
CC
+ 0.75V DC
which may overshoot to +7.0V for pulses of less
than 20 ns.
Operating Modes
Mode/Pin
Read
(2)
Output Disable
(2)
Standby
Address Latch Enable
(2)
Rapid Program
(3)
Product Identification
(4)
Notes:
1. X can be V
IL
or V
IH.
2. Read, output disable, and standby modes require 3.0V
≤
V
CC
≤
3.6V, or 4.5V
≤
V
CC
≤
5.5V.
3. Refer to Programming Characteristics.
4. V
H
= 12.0
±
0.5V.
5. Two identifier bytes may be selected. All A8 - A15 inputs are held low (V
IL
), except A9 which is set to V
H
and A8 which is tog-
gled low (V
IL
) to select the Manufacturer’s Identification byte and high (V
IH
) to select the Device Code byte.
ALE
V
IL
V
IL
/V
IH
V
IH
V
IH
V
IH
V
IL
OE/V
PP
V
IL
V
IH
V
IH
V
IH
V
PP
V
IL
A8 - A15
Ai
X
(1)
Ai
X
Ai
A9 = V
H(5)
A8 = V
IH
or V
IL
A10 - A15 = V
IL
AD0 - AD7
D
OUT
High Z/A0 - A7
A0 - A7
A0 - A7
D
IN
Identification Code
3
DC and AC Operating Conditions for Read Operation
AT27LV520-90
Com.
Operating Temp. (Case)
Ind.
V
CC
Supply
-40°C - +85°C
3.0V to 3.6V
5V
±
10%
0°C - 70°C
DC and Operating Characteristics for Read Operation
Symbol
Parameter
Condition
Min
Max
Units
V
CC
= 3.0V to 3.6V
I
LI
I
LO
I
SB (1)
I
CC
V
IL
V
IH
V
OL
V
OH
Input Load Current
Output Leakage Current
V
CC
Standby Current
V
CC
Active Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I
OL
= 2.0 mA
I
OH
= -2.0 mA
2.4
V
IN
= 0V to V
CC
V
OUT
= 0V to V
CC
ALE = V
CC
±
0.3V; Ai, ADi = GND/V
CC
±
0.3V
f = 5 MHz, I
OUT
= 0 mA, ALE = V
IL
-0.6
2.0
±1
±5
20
8
0.8
V
CC
+ 0.5
0.4
µA
µA
µA
mA
V
V
V
V
V
CC
= 4.5V to 5.5V
I
LI
I
LO
I
SB (1)
I
CC
V
IL
V
IH
V
OL
V
OH
Input Load Current
Output Leakage Current
V
CC
Standby Current
V
CC
Active Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I
OL
= 2.1 mA
I
OH
= -400
µA
2.4
V
IN
= 0V to V
CC
V
OUT
= 0V to V
CC
ALE = V
CC
±
0.3V; Ai, ADi = GND/V
CC
±
0.3V
f = 5 MHz, I
OUT
= 0 mA, ALE = V
IL
-0.6
2.0
±1
±5
100
20
0.8
V
CC
+ 0.5
0.4
µA
µA
µA
mA
V
V
V
Note:
V
CC
standby current will be slightly higher with ALE, Ai, and ADi at TTL levels.
AC Characteristics for Read Operation
V
CC
= 3.0V to 3.6V and 4.5V to 5.5V
AT27LV520-90
Symbol
t
ACC(3)
t
CE
tAS
tAH
tALE
t
OE(3)
t
DF(4)(5)
t
OH
Parameter
Address to Output Delay
Address Latch Enable Low to Output Delay
Address Setup Time
Address Hold Time
Address Latch Enable Width
OE/V
PP
to Output Delay
OE/V
PP
High to Output Float
Output Hold from Address or OE/V
PP
whichever occurred first
,
Condition
ALE = OE/V
PP
= V
IL
Address Valid
OE/VPP = VIH
OE/VPP = VIH
OE/VPP = VIH
ALE = V
IL
ALE = V
IL
ALE = V
IL
0
15
15
45
35
25
Min
Max
90
70
Units
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
2, 3, 4 — see AC Waveforms for Read Operation
4
AT27LV520
AT27LV520
AC Waveforms for Read Operation
(1)
tALE
ALE
tCE
OE/V
PP
tDF
tAS
AD7 - AD0
ADDRESS IN
tACC
A15 - A8
Notes:
1.
2.
3.
4.
5.
Timing measurement reference levels for all speed grades are V
OL
= 0.8V and V
OH
= 2.0V. Input AC drive levels are V
IL
=
0.45V and V
IH
= 2.4V.
OE/V
PP
may be delayed up to t
CE
- t
OE
after the address is valid without impact on t
CE
.
OE/V
PP
may be delayed up to t
ACC
- t
OE
after the address is valid without impact on t
ACC
.
This parameter is only sampled and is not 100% tested.
Output float is defined as the point when data is no longer driven.
tAH
tOE
tOH
DATA OUT
Input Test Waveforms and Measurement Levels
Output Test Load
t
R
, t
F
< 20 ns (10% to 90%)
Note:
C
L
= 100 pF including jig
capacitance.
Pin Capacitance
(Note:)
(f = 1 MHz, T = 25°C)
Typ
C
IN
C
OUT
Note:
Max
6
12
Units
pF
pF
Conditions
V
IN
= 0V
V
OUT
= 0V
4
8
Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
5
京公网安备 11010802033920号
EEWORLD
