Integrated
Circuit
Systems, Inc.
Preliminary Information
VCSO FEC PLL
FOR
SONET/OTN
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
FIN_SEL1
GND
P_SEL2
DIF_REF0
nDIF_REF0
REF_SEL
DIF_REF1
nDIF_REF1
VCC
FIN_SEL0
FEC_SEL0
FEC_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
27
26
25
24
23
22
21
20
19
M2060/61/62
M2065/66/67
G
ENERAL
D
ESCRIPTION
The M2060/61/62 and M2065/66/67 are VCSO (Voltage
Controlled SAW Oscillator) based
clock PLLs designed for FEC clock
ratio translation in 10Gb optical
systems such as OC-192 or 10GbE.
They support FEC (Forward Error
Correction) clock multiplication
ratios, both forward (mapping) and
inverse (de-mapping). Multiplication ratios are
pin-selected from pre-programming look-up tables.
F
EATURES
◆
Integrated SAW delay line; Output of 15 to 700 MHz
*
◆
Low phase jitter < 0.5 ps rms typical
(12kHz to 20MHz or 50kHz to 80MHz)
◆
Pin-selectable PLL divider ratios support FEC ratios
• M2060/65: OTU1 (255/238) and OTU2 (255/237) Mapping
• M2061/66: OTU1 (238/255) or OTU2 (237/255) De-mapping
• M2062/67: OTU1 (238/255)
and
OTU2 (237/255) De-mapping
28
29
30
31
32
33
34
35
36
M2060
Series
(Top View)
18
17
16
15
14
13
12
11
10
P_SEL0
P_SEL1
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
Figure 1: Pin Assignment
◆
LVPECL clock output (CML and LVDS options available)
◆
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆
Loss of Lock (LOL) output pin
◆
Narrow Bandwidth control input (NBW pin) to adjust
loop bandwidth
◆
Hitless Switching (HS) options with or without Phase
Build-out (PBO) available to enable SONET (GR-253)
/SDH (G.813) MTIE and TDEV compliance during
reference clock reselection
◆
Single 3.3V power supply
◆
Small 9 x 9 mm SMT (surface mount) package
Example I/O Clock Frequency Combinations
Using M2061-11-622.0800 FEC De-Map Ratios
FEC De-Map
PLL Ratio
Mfec / Rfec
1/1
237/255
238/255
Base Input Rate
1
(MHz)
622.0800
666.5143
669.3266
Output Clock
(either output)
MHz
622.08
or
155.52
Table 1: Example I/O Clock Frequency Combinations
Note 1: Input reference clock can be the base frequency shown
divided by “Mfin” (as shown in Tables 3 and 4 on pg. 3).
* Specify VCSO center frequency at time of order.
S
IMPLIFIED
B
LOCK
D
IAGRAM
Loop
Filter
M2060 Series
NBW
LOL
MUX
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_SEL
FEC_SEL1:0
FIN_SEL1:0
P_SEL2:0
2
0
1
Rfec
Div
Phase
Detector
VCSO
Mfec Div
Mfec and Rfec
Divider
LUT
Mfin Divider
LUT
(1, 4, 8, 32)
or
( 1, 4, 8, 16)
Mfin Div
GND
GND
GND
OP_IN
nOP_OUT
nVC
VC
OP_OUT
nOP_IN
1
2
3
4
5
6
7
8
9
P Divider
FOUT0: 1, 4, 8, 32 or TriState
FOUT1: 1, 4, 8 or TriState
TriState
FOUT0
nFOUT0
FOUT1
nFOUT1
2
3
P Divider
LUT
Figure 2: Simplified Block Diagram
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
M2060/61/62 VCSO FEC PLL for SONET/OTN
Revised 30Jul2004
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Integrated
Circuit
Systems, Inc.
M2060/61/62, M2065/66/67
VCSO FEC PLL
FOR
SONET/OTN
Preliminary Information
P
IN
D
ESCRIPTIONS
Number
1, 2, 3, 10, 14, 26
4
9
5
8
6
7
11, 19, 33
12
13
15
16
17
18
25
20
21
22
23
24
27
28
29
30
31
Name
GND
OP_IN
nOP_IN
nOP_OUT
OP_OUT
nVC
VC
VCC
FOUT1
nFOUT1
FOUT0
nFOUT0
P_SEL1
P_SEL0
P_SEL2
nDIF_REF1
DIF_REF1
REF_SEL
nDIF_REF0
DIF_REF0
FIN_SEL1
FIN_SEL0
FEC_SEL0
FEC_SEL1
LOL
I/O
Configuration
Description
Ground
Input
Output
Input
Power
Output
Output
Input
Input
Input
Input
Input
Input
No internal terminator
No internal terminator
Power supply ground connections.
External loop filter connections.
See Figure 5, External Loop Filter, on pg. 8.
Power supply connection, connect to +
3.3
V.
Clock output pair 1. Differential LVPECL.
Clock output pair 0. Differential LVPECL.
, P divider selection. LVCMOS/LVTTL. See Table 8,
Internal pull-down resistor
1
Post-PLL Look-Up Table (LUT), on pg. 4.
P Divider
Biased to Vcc/2
2
Internal pull-down resistor
1
Internal pull-down resistor
1
Biased to Vcc/2
2
Internal pull-down resistor
1
Reference clock input pair 1. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
Reference clock input selection. LVCMOS/LVTTL:
Logic
1
selects
DIF_REF1, nDIF_REF1.
Logic
0
selects
DIF_REF0, nDIF_REF0
.
Reference clock input pair 0. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
I
nput clock frequency selection. LVCMOS/LVTTL. See
Internal pull-down resistor
1
Tables
3
and
4
Mfin Divider Look-Up Tables (LUT) on pg. 3.
Mfec and Rfec divider value selection. LVCMOS/ LVTTL.
Internal pull-down resistor
1
See Tables 5, 6, and
7 on pg. 3.
Output
32
34, 35, 36
NBW
DNC
Input
Internal pull-UP resistor
1
Do Not Connect.
Loss of Lock indicator output. Asserted when internal PLL is
not tracking the input reference for frequency and phase.
3
Logic
1
indicates loss of lock.
Logic
0
indicates locked condition.
Narrow Bandwidth enable. LVCMOS/LVTTL:
Logic
1
- Narrow loop bandwidth
, R
IN
= 2100kΩ
.
Logic
0
- Wide bandwidth
, R
IN
= 100kΩ
.
Internal nodes. Connection to these pins can cause erratic
device operation.
Table 2: Pin Descriptions
Note 1: For typical values of internal pull-down and pull-UP resistors, see
DC Characteristics
on pg. 10.
Note 2: Biased toVcc/2, with 50kΩ to Vcc and 50kΩ to ground. See
Differential Inputs Biased to VCC/2
on pg. 10.
Note 3: See
LVCMOS Output
in
DC Characteristics
on pg. 10.
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
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Integrated
Circuit
Systems, Inc.
M2060/61/62, M2065/66/67
VCSO FEC PLL
FOR
SONET/OTN
Preliminary Information
D
ETAILED
B
LOCK
D
IAGRAM
R
LOOP
C
LOOP
R
POST
C
POST
C
POST
R
LOOP
C
LOOP
OP_OUT
R
POST
nOP_OUT
nVC
VC
External
Loop Filter
Components
M2060 Series
NBW
LOL
MUX
Phase
Detector
Rfec
Div
OP_IN
nOP_IN
Hitless Switching (HS) Opt.
HS with Phase Build-out Opt.
R
IN
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_SEL
0
R
IN
1
Loop Filter
Amplifier
Mfin Divider
1,4,8,32 Options
Phase
Locked
Loop
(PLL)
SAW Delay Line
Phase
Shifter
VCSO
Mfec Div
FEC_SEL1:0
Mfec/Rfec Divider
LUT
P Divider
1,4,8,32
Options
TriState
FOUT0
nFOUT0
FOUT1
nFOUT1
FIN_SEL1:0
Mfin Divider
LUT
P Divider
LUT
P_SEL2:0
Figure 3: Detailed Block Diagram
D
IVIDER
S
ELECTION
T
ABLES
Mfin Divider Look-Up Tables (LUT)
The
FIN_SEL1:0
pins select the feedback divider value
(“Mfin”), which sets the overall PLL ratio range. Since
the VCSO frequency is fixed, this allows input reference
selection. The look-up tables vary by device variant.
M2060/61/62: Mfin Value LUT (Includes Divide by 32)
FIN_SEL1:0
Mfec and Rfec Divider Look-Up Tables (LUTs)
The
FEC_SEL
pins select the Mfec/Rfec divider ratio. The
look-up tables vary by device variant. The Mfec and
Rfec values also establish phase detector frequency.
A lower phase detector frequency improves jitter
tolerance and lowers loop bandwidth.
M2060/65: FEC Map LUT, OTU1 (255/238) and OTU2 (255/237)
FEC_SEL1:0
Mfec Rfec
1 0
Description
Mfin Sample Input Reference Freq. (MHz) Options
For
M2060
1
,
M2061
&
M2062
2
Value
Fvcso =
Base Input Base Output
Rate (MHz)
Rate (MHz)
For
M2060 or M2065 with Fvcso = 666.5143
(OTU1 FEC rate):
0
0
1
1
0
1
0
1
32
8
4
1
19.44
77.76
155.52
622.08
0
0
1
1
0
1
0
1
15 14
15 15
85 79
85 85
255/238
OC-48 to OTU1 encode
OTU1 repeater or jitter attenuator
622.08 666.5143
666.5143 666.5143
622.08 669.3266
669.3266 669.3266
For
M2060 or M2065 with Fvcso = 669.3266
(OTU2 FEC rate):
255/237
OC-192 to OTU2 encode
OTU2 repeater or jitter attenuator
Table 3: M2060/61/62: Mfin Value LUT (Includes Divide by 32)
Note 1: For M2060 with Fvcso = 666.5143 or 669.3266
Note 2: For M2061 and M2062 with Fvcso = 622.0800.
Table 5: M2060/65: FEC Map LUT, OTU1 (255/238) and OTU2 (255/237)
M2065/66/67: Mfin Value LUT (Includes Divide by 16)
FIN_SEL1:0
M2061/66: FEC De-map LUT, OTU1 (238/255) or OTU2 (237/255)
Mfin Sample Input Reference Freq. (MHz) Options
For
M2065
1
,
M2066
&
M2067
2
Value
Use this option for
either
OTU1
or
OTU2 de-mapping
applications, but not both.
FEC_SEL1:0
Mfec Rfec
1 0
0
0
1
1
0
1
0
1
16
8
4
1
38.88
77.76
155.52
622.08
Description
Fvcso =
Base Input Base Output
Rate (MHz) Rate (MHz)
For
M2061 or M2066 with Fvcso = 622.08
(OTU1 or OTU2 FEC rate):
Table 4: M2065/66/67: Mfin Value LUT (Includes Divide by 16)
0
0
1
1
0
1
0
1
79 85
79 79
14 15
14 14
237/255
OTU2 to OC-192 decode
OC-192 repeater or jitter attenuator
238/255
OTU1 to OC-48 decode
OC-48 repeater or jitter attenuator
669.3266
622.08
666.5143
622.08
622.08
622.08
622.08
622.08
Note 1: For M2065 with Fvcso = 666.5143 or 669.3266
Note 2: For M2066 and M2067 with Fvcso = 622.0800.
Table 6: M2061/66: FEC De-map LUT, OTU1 (238/255) or OTU2 (237/255)
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
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M2062/67: FEC De-map LUT, Both OTU1 and OTU2
M2060/61/62, M2065/66/67
VCSO FEC PLL
FOR
SONET/OTN
Preliminary Information
F
UNCTIONAL
D
ESCRIPTION
The M206x Series is a PLL (Phase Locked Loop) based
clock generator that generates output clocks synchro-
nized to one of two selectable input reference clocks.
An internal high "Q" SAW delay line provides low jitter
signal performance and establishes the output
frequency of the VCSO (Voltage Controlled SAW
Oscillator). In a given M206x Series device, the VCSO
center frequency is fixed. A common center frequency
is
622.08MHz,
for SONET or SDH optical network
applications. The VCSO center frequency is specified at
time of order (see “Ordering Information” on pg. 12).
The VCSO has a guaranteed tuning range of
±120
ppm
(commercial temperature grade).
Pin selectable dividers are used within the PLL and
for the output clock. This enables tailoring of device
functionality and performance. The FEC feedback and
reference dividers (the “Mfec Divider” and “Rfec
Divider”) provide the multiplication ratios necessary to
accomodate clock translation for both forward and
inverse Forward Error Correction. The Mfec and Rfec
dividers also control the phase detector frequency. The
feedback divider (labeled “Mfin Divider”) provides the
broader division options needed to accomodate various
reference clock frequencies.
For example, the
M2062-11-622.0800
(see “Ordering
Information”
on pg. 12
)
has a
622.08
MHz VCSO
frequency:
Use this option for
both
OTU1 or OTU2 de-mapping
applications. The Mfec divider value is kept nearly
constant to maintain similar loop bandwidth using one
set of external filter component values.
FEC_SEL1:0
Mfec Rfec
1 0
Description
Fvcso =
Base Input
Base Output
Rate (MHz)
Rate (MHz)
For
M2062 or M2067 with Fvcso = 622.08
(OTU1 or OTU2 FEC rate):
0
0
1
1
0
1
0
1
79 85
79 79
84 90
84 84
237/255
OTU2 to OC-192 decode
OC-192 repeater or jitter attenuator
238/255
OTU1 to OC-48 decode
OC-48 repeater or jitter attenuator
669.3266
622.08
666.5143
622.08
622.08
622.08
622.08
622.08
Table 7: M2062/67: FEC De-map LUT, Both OTU1 and OTU2
P Divider Look-Up Table (LUT)
The
P_SEL2:0
pins select the P divider values, which set
the output clock frequencies. P divider values of
1
,
4
,
8
,
or
32
are available, plus a TriState mode. A P divider of
value of
1
will provide a
669.3266MHz
output when using
a
669.3266MHz
VCSO, for example. The outputs can be
placed into the valid state combinations as listed in
Table 8. (They cannot be set independently to any of the
available output frequencies.)
P Value
P_SEL2:0
M2060-622.0800 or M2065-622.0800
for
FOUT0
for
FOUT1
32
1
32
4
1
1
4
1
8
8
4
4
8
4
TriState TriState
Output Frequency (MHz)
FOUT0
FOUT1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
19.44
19.44
622.08
155.52
77.76
155.52
77.76
N/A
622.08
155.52
622.08
622.08
77.76
155.52
155.52
N/A
•
The FEC de-mapper PLL ratios (in Tables 6 and
7)
enable the
M2062-11-622.0800
to accept “base” input
reference frequencies of:
666.5143 (OTU1)
,
669.3266
(OTU2)
, and
622.08
MHz
(OC-192)
.
•
The Mfin feedback divider enables the actual input
reference clock to be the base input frequency
divided by
1
,
4
,
8
, or
32 (or 16)
. Therefore, for the base
input frequency of
622.08
MHz, the actual input
reference clock frequencies can be:
622.08
,
155.52
,
77.76
, and
19.44 or 38.88
MHz. (See Tables 3 and 4 on
pg. 3.)
Key to Device Variants and Look-up Table Options
Device
Variant
M2060
M2061
M2062
M2065
M2066
M2067
Look-up Table Option
Mfin Lookup Table is:
Mfec Look-up Table is:
Table 5
(FEC mapper LUT)
Table 3
Table 6
(FEC de-mapper LUT)
(includes divider value 32)
Table 7
(FEC de-mapper LUT)
Table 5
(FEC mapper LUT)
Table 4
Table 6
(FEC de-mapper LUT)
(includes divider value 16)
Table 7
(FEC de-mapper LUT)
Table 9: Key to Device Variants and Look-up Table Options
Table 8: P Divider Look-Up Table (LUT)
General Guidelines for Phase Detector Frequency
The phase detector frequency (Fpd) is equal to the
input reference frequency (Fref) divided by the Rfec
divider value, or:
Fpd = Fref / Rfec
General guidelines:
•
A lower phase detector frequency should be used for
loop timing applications to assure PLL tracking,
especially during GR-253 jitter tolerance testing. The
recommended maximum phase detector frequency
for loop timing mode is
19.44
MHz.
•
When
LOL
is to be used for system health monitoring,
the phase detector frequency should be 5MHz or
greater. Low phase detector frequencies make
LOL
overly sensitive, and higher phase detector
frequencies make
LOL
less sensitive. The
LOL
pin
should not be used during loop timing mode.
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
●
The P divider scales the VCSO output enabling lower
output frequency selections (Table 8).
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The M206x Series includes a Loss of Lock (
LOL
)
indicator, which provides status information to system
management software. A Narrow Bandwidth (
NBW
)
control pin is provided as an additional mechanism for
adjusting PLL loop bandwidth without affecting the
phase detector frequency.
Options are available for Hitless Switching (HS) with or
without Phase Build-out (PBO). They provide SONET/
SDH MTIE and TDEV compliance during a reference
clock reselection.
Input Reference Clocks
Two clock reference inputs and a selection mux is
provided. Either reference clock input can accept a
differential clock signal (such as LVPECL or LVDS) or
a single-ended clock input (LVCMOS or LVTTL on the
non-inverting input).
A single-ended reference clock on the unselected
reference input can cause an increase in output
clock jitter. For this reason, differential reference
inputs are preferred; interference from a differential
input on the non-selected input is minimal.
M2060/61/62, M2065/66/67
VCSO FEC PLL
FOR
SONET/OTN
Preliminary Information
Differential Inputs
Differential LVPECL inputs are connected to both
reference input pins in the usual manner. The external
load termination resistors shown in Figure 4 (the
127
Ω
and
82
Ω
resistors) is ideally suited for both AC and DC
coupled LVPECL reference clock lines. These provide
the
50
Ω
load termination and the VTT bias voltage.
Single-ended Inputs
Single-ended inputs (LVCMOS or LVTTL) are
connected to the non-inverting reference input pin
(
DIF_REF0
or
DIF_REF1
). The inverting reference input pin
(
nDIF_REF0
or
nDIF_REF1
) must be left unconnected.
In single-ended operation, when the unused inverting
input pin (nDIF_REF0 or
nDEF_REF1)
is left floating (not
connected), the input will self-bias at VCC/2.
PLL Operation
The M2060/61/62 and M2065/66/67 are complete clock
PLLs. They use a phase detector and configurable
dividers to synchronize the output of the VCSO with the
selected reference clock.
The PLL will work correctly, meaning it will phase-lock
the VCSO output to the input reference clock, when the
internal phase detector inputs are able to run at the
same frequency. This means the PLL dividers must be
set appropriately and a suitable reference frequency
must be chosen for the intended output frequency.
When the PLL is not set up appropriately, the VCSO is
forced to its upper or lower operating limit which is typi-
cally about 200 ppm above or below the VCSO center
frequency. See “APR, VCSO Absolute Pull-Range” row,
in the AC Characteristics table on pg. 11.
In normal phase-locked condition, the instantaneous
phase error is measured by the phase detector and is
converted to charge pump current pulses. These
current pulses are then integrated by the external loop
filter to create a VCSO control voltage. The loop filter
acts as a low pass filter to remove unwanted reference
clock jitter above a determined frequency or PLL
bandwidth. For reference phase jitter frequencies within
the loop bandwidth, phase jitter amplitude is passed on
to the output clock according to the PLL loop frequency
response curve.
The relationship between the nominal VCSO center
frequency (Fvcso), the Mfin divider, the Mfec divider,
the Rfec divider, and the input reference frequency (Fin)
is:
Mfec
-
Fvcso
=
Fin
×
Mfin
×
-------------
Rfec
Configuration of a single-ended input has been
facilitated by biasing
nDIF_REF0
and
nDEF_REF1
to Vcc/2,
with 50kΩ to Vcc and 50kΩ to ground. The input clock
structure, and how it is used with either
LVCMOS/LVTTL inputs or a DC- coupled LVPECL
clock, is shown in Figure 4.
.
DIF_REF0
50k
Ω
VCC
50k
Ω
X
50k
Ω
MUX
LVCMOS/
LVTTL
nDIF_REF0
VCC
0
DIF_REF1
LVPECL
127
Ω
VCC
127
Ω
VCC
50k
Ω
1
82
Ω
50k
Ω
nDIF_REF1
REF_SEL
82
Ω
50k
Ω
Figure 4: Input Reference Clocks
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
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