935291474115 datasheet, PDF - EEWORLD Datasheet

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935291474115: DescriptionNOR Gate, AUP/ULP/V Series, 2-Func, 2-Input, CMOS, PDSO8; Categorylogic logic; File Size320KB，21 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com; Environmental Compliance

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935291474115 Overview

NOR Gate, AUP/ULP/V Series, 2-Func, 2-Input, CMOS, PDSO8

935291474115 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Nexperia
package instruction	VSON,
Reach Compliance Code	compli
series	AUP/ULP/V
JESD-30 code	R-PDSO-N8
JESD-609 code	e3
length	1.35 mm
Logic integrated circuit type	NOR GATE
Humidity sensitivity level	1
Number of functions	2
Number of entries	2
Number of terminals	8
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	VSON
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, VERY THIN PROFILE
propagation delay (tpd)	24.7 ns
Maximum seat height	0.5 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	0.8 V
Nominal supply voltage (Vsup)	1.1 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Tin (Sn)
Terminal form	NO LEAD
Terminal pitch	0.35 mm
Terminal location	DUAL
width	1 mm

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74AUP2G02

Low-power dual 2-input NOR gate

Rev. 7 — 4 February 2013

Product data sheet

1. General description

The 74AUP2G02 provides a dual 2-input NOR function.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire V

range from 0.8 V o 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire

range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using I

OFF

. The I

OFF

circuitry disables the output, preventing a damaging backflow current through the device

when it is powered down.

2. Features and benefits



Wide supply voltage range from 0.8 V to 3.6 V



High noise immunity



Complies with JEDEC standards:



JESD8-12 (0.8 V to 1.3 V)



JESD8-11 (0.9 V to 1.65 V)



JESD8-7 (1.2 V to 1.95 V)



JESD8-5 (1.8 V to 2.7 V)



JESD8-B (2.7 V to 3.6 V)



ESD protection:



HBM JESD22-A114F Class 3A exceeds 5000 V



MM JESD22-A115-A exceeds 200 V



CDM JESD22-C101E exceeds 1000 V



Low static power consumption; I

= 0.9

A

(maximum)



Latch-up performance exceeds 100 mA per JESD78B Class II



Inputs accept voltages up to 3.6 V



Low noise overshoot and undershoot < 10 % of V



OFF

circuitry provides partial power-down mode operation



Multiple package options



Specified from

40 C

to +85

C

and

40 C

to +125

C

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