EURO
QUARTZ
Frequency range 38MHz to 640MHz
LVDS Output
Supply Voltage 3.3 VDC
Phase jitter 0.4ps typical
Pull range from ±30ppm to ±150ppm
GDF64 LVDS VCXO
11.4 x 9.6 x 4.7mm SMD VCXO
DESCRIPTION
GDF64 VCXOs are packaged in a 6 pad 11.4 x 9.6m SMD package.
Typical phase jitter for GDF series VCXOs is 0.4 ps. Output is LVDS.
Applications include phase lock loop, SONET/ATM, set-top boxes,
MPEG , audio/video modulation, video game consoles and HDTV.
OUTLINE & DIMENSIONS
SPECIFICATION
Frequency Range:
Supply Voltage:
Output Logic:
RMS Period Jitter:
Peak to Peak Jitter:
Phase Jitter:
Initial Frequency Accuracy:
Output Voltage HIGH (1):
Output Voltage LOW (0):
Pulling Range:
Control Voltage Range:
Temperature Stability:
Output Load:
Rise/Fall Times:
Duty Cycle:
Start-up Time:
Current Consumption:
Static Discharge Protection:
Storage Temperature:
Ageing:
Enable/Disable:
RoHS Status:
38.0MHz to 640.0MHz
3.3 VDC ±5%
LVDS
3.0ps typical
20.0ps typical, 30.0ps maximum
0.4ps typical, 5.0ps maximum
Tune to the nominal frequency
with Vc= 1.65 ±0.2VDC
1.4 Volts typical
1.1 Volts typical
From ±30ppm to ±150ppm
1.65 ±1.35 Volts
See table
50 into Vdd or Thevenin equiv.
0.5ns typ., 0.7ns max.
20% Vdd to 80% Vdd
50% ±5%
(Measured at Vdd-1.3V)
10ms maximum, 5ms typical
55mA typical, 60mA maximum
(At 202.50MHz)
2kV maximum
-55° to +150°C
±2ppm per year maximum
See table
Fully compliant or non compliant
FREQUENCY STABILITY
Stability Code Stability ±ppm Temp. Range
A
25
0°~+70°C
B
50
0°~+70°C
C
100
0°~+70°C
D
25
-40°~+85°C
E
50
-40°~+85°C
F
100
-40°~+85°C
If non-standard frequency stability is required
Use ‘I’ followed by stability, i.e. I20 for ±20ppm
PART NUMBERING
Example:
Supply Voltage
3 = +3.3V
Series Designator
GDF64
RoHS Status
G = Compliant
Blank - Non-compliant
Stability over temperature range
(See table)
Pullability in ±ppm
Pullability determinator
N = minimum
M = maximum
T = Typical
Frequency in MHz
3GDF64GB-80N-60.000
ENABLE/DISABLE FUNCTION
Tristate Pad
Status
Not connected
Below 0.3Vdd
(Ref. to ground)
Above 0.7Vdd
(Ref. to ground)
Output Status
LVDS and Complimentary LVDS enabled
Both outputs are disabled (high impedance)
Both outputs are enabled
EUROQUARTZ LIMITED Blacknell Lane CREWKERNE Somerset UK TA18 7HE
Tel: +44 (0)1460 230000 Fax: +44 (0)1460 230001 Email: info@euroquartz.co.uk www.euroquartz.co.uk
FPGA/CPLD
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