A32200DXV-FRQ240C datasheet, PDF

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A32200DXV-FRQ240C: DescriptionField Programmable Gate Array, 1230 CLBs, 20000 Gates, CMOS, PQFP240, HEAT SINK, POWER, PLASTIC, RQFP-240; CategoryProgrammable logic devices Programmable logic; File Size457KB，82 Pages; ManufacturerActel; Websitehttp://www.actel.com/

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A32200DXV-FRQ240C Overview

Field Programmable Gate Array, 1230 CLBs, 20000 Gates, CMOS, PQFP240, HEAT SINK, POWER, PLASTIC, RQFP-240

A32200DXV-FRQ240C Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Actel
package instruction	HEAT SINK, POWER, PLASTIC, RQFP-240
Reach Compliance Code	compli
Combined latency of CLB-Max	5.2 ns
JESD-30 code	S-PQFP-G240
JESD-609 code	e0
length	32 mm
Humidity sensitivity level	4
Configurable number of logic blocks	1230
Equivalent number of gates	20000
Number of terminals	240
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1230 CLBS, 20000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	HFQFP
Package shape	SQUARE
Package form	FLATPACK, HEAT SINK/SLUG, FINE PITCH
Peak Reflow Temperature (Celsius)	225
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	4.1 mm
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	32 mm

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Integrator Series FPGAs

– 1200XL and 3200DX Familes

Fe atur es

High Capacity

•

2,500 to 40,000 logic gates

Up to 4 Kbits configurable dual-port SRAM

Fast wide-decode circuitry

Up to 288 user-programmable I/O Pins

225 MHz performance

5 ns Dual-Port SRAM Access

100 MHz FIFOs

7.5 ns 35-bit Address Decode

Cadence, Escalade, Exemplar, IST, Mentor Graphics,

Synopsys and Viewlogic

• JTAG 1149.1 Boundary Scan Testing

Ge ne r al D e s c r ip t i on

High Performance

Actel’s Integrator Series FPGAs are the first programmable

logic devices optimized for high-speed system logic

integration. Based on Actel's proprietary PLICE antifuse

technology and state-of-the-art 0.6-micron double metal

CMOS process, the Integrator Series devices offer a

fine-grained, register-rich architecture with the industry’s

fastest embedded dual-port SRAM and wide decode circuitry.

3200DX and 1200XL FPGAs were designed to integrate

system logic which is typically implemented in multiple

CPLDs, PALs and FPGAs. These devices provide the features

and performance required for today’s complex, high-speed

digital logic systems. The 3200DX family offers the industry’s

fastest dual-port SRAM for implementing fast FIFOs, LIFOs

and temporary data storage. The large number of storage

elements can efficiently address applications requiring wide

datapath manipulation and transformation functions such as

telecommunications, networking and DSP.

Ease-of-Integration

• Synthesis-friendly architecture supports ASIC design

methodologies

• 95–100% device utilization using automatic Place and

Route Tools

• Deterministic, user-controllable timing via DirectTime

software tools

• Supported by Actel Designer Series development system

with interfaces to popular design environments such as

In tegr ato r Seri es Product Pro fil e

Device

Capacity

A1225XL

A1240XL

A3265DX

A1280XL

A32100DX A32140DX A32200DX A32300DX A32400DX

Logic Gates

SRAM Bits

Logic Modules

2,500

N/A

231

220

N/A

231

PL84

PQ100

VQ100

PG100

4,000

N/A

348

336

N/A

348

104

PL84

PQ100

PQ144

TQ176

PG132

6,500

N/A

510

475

510

126

PL84

PQ100

PQ160

TQ176

8,000

N/A

624

608

N/A

624

140

PL84

PQ160

PQ208

TQ176

PG176

CQ172

10,000

2,048

700

662

700

152

Yes

PL84

PQ160

PQ208

TQ176

CQ84

14,000

N/A

954

912

954

176

Yes

PL84

PQ160

PQ208

TQ176

CQ256

20,000

2,560

1,230

1,184

1,230

202

Yes

PQ208

RQ208

RQ240

CQ208

CQ256

30,000

3,072

1,888

1,833

1,888

250

Yes

RQ208

RQ240

CQ256

40,000

4,096

2,526

2,466

2,526

288

Yes

RQ240

Sequential

Combinatorial

Decode

SRAM Modules

(64x4 or 32x8)

Dedicated Flip-Flops

Clocks

User I/O

(maximum)

JTAG

Packages

Note 1:

Logic gate capacity does not include SRAM bits as logic.

S e p t e m b e r 19 9 7

1-9

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