D2516EC4BXGGB-U datasheet, PDF

Datasheet> All Categories > storage> storage> D2516EC4BXGGB-U

D2516EC4BXGGB-U: DescriptionDDR DRAM, 256MX16, CMOS, PBGA96, FBGA-96; Categorystorage storage; File Size639KB，1 Pages; ManufacturerKingston; Websitehttps://www.kingston.com/cn; Environmental Compliance

Download Datasheet Parametric View All

D2516EC4BXGGB-U Overview

DDR DRAM, 256MX16, CMOS, PBGA96, FBGA-96

D2516EC4BXGGB-U Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Kingston
package instruction	BGA,
Reach Compliance Code	compli
Other features	SELF REFRESH
JESD-30 code	R-PBGA-B96
memory density	4294967296 bi
Memory IC Type	DDR DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	96
word count	268435456 words
character code	256000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	95 °C
Minimum operating temperature
organize	256MX16
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
self refresh	YES
Nominal supply voltage (Vsup)	1.35 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED

Preview

Download Datasheet

View All

KINGSTON.COM

Kingston DDR3/3L DRAM

for embedded applications

Kingston DDR3/3L

Kingston on-board DRAM is designed to meet the needs of embedded applications

and offers a low-voltage option for lower power consumption.

DDR3/3L Part Numbers and Specifications

DDR3/3L Part

Number

D2516EC4BXGGB

D5128EETBPGGBU

Capacity

4Gb

Description

96 ball FBGA

DDR3/3L

78 ball FBGA

DDR3/3L

Package

Size

9.0x13.5x1.2

9.0x10.6x1.2

Organization

(words x bits)

256MX16

512Mx8

Speed

Mbps

1600

VDD,

VDDQ

1.35V*

Operating

Temperature

0°C ~ +95°C

*Backward compatible to 1.5V VDD, VDDQ

Features

• Double-data-rate architecture: two data transfers per clock cycle

• The high-speed data transfer is realized by the 8 bits prefetch pipelined

architecture

• Bi-directional differential data strobe (DOS and /DQS) is transmitted/received

with data for capturing data at the receiver

• DOS is edge-aligned with data for READS; center-aligned with data for WRITES

• Differential clock inputs (CK and !CK)

• DLL aligns DQ and DOS transitions with CK transitions

• Commands entered on each positive CK edge; data and data mask referenced

to both edges of DQS

• Data mask (DM) for write data

• Posted /CAS by programmable additive latency for better command and data

bus efficiency

• On-Die Termination (ODD for better signal quality

— Synchronous ODT

— Dynamic CDT

Asynchronous ODT

• Multi Purpose Register (MPR) for pre-defined pattern read out

• ZQ calibration for DO drive and ODT

• Programmable Partial Array Self-Refresh (PASR)

• /RESET pin for Power-up sequence and reset function

• SRT range: Normal/extended

• Programmable Output driver impedance control

THIS DOCUMENT SUBJECT TO CHANGE WITHOUT NOTICE

Recommended Resources

Motor inching operation circuit

Current limited circuit diagram

AN7178 power amplifier circuit diagram

Multipurpose parallel monitoring circuit

380V 50Hz 3A phase sequence fixed circuit

Voice-controlled music socket circuit made with SK-Ⅱ

How to set the coordinate mapping method in EVC: The coordinate mapping method in vc++ can be set directly through SetMapMade(), but EVC drawing cannot. How can I solve this problem? ? ? Thank you...; nwuwmz Embedded System

Principles and requirements for the 2009 National Undergraduate Electronic Design Competition: [i=s]This post was last edited by paulhyde on 2014-9-15 09:30[/i][b][font=华文中宋][size=16pt][font=宋体]I. Principles and requirements of proposition[/font][/size][/font][/b] [font=宋体][font=新宋体-18030][size...; open82977352 Electronics Design Contest

A small problem in the FPGA course design, please help me take a look...: Recently, the teacher assigned a course design to realize a music jukebox using FPGA. Store 3 music scores in ROM, and then switch songs by pressing buttons. The specific requirements are as follows: ...; panxiao FPGA/CPLD

In the ECG common mode rejection ratio test, why is a 20Vrms/50Hz sinusoidal signal selected as the test signal?: As the title says, I have looked at the common mode rejection ratio test schemes of YY1139 and IEC60601-2-25 before. I don’t quite understand why the 20Vrms/50Hz sine test signal is selected. I would ...; dswu233 Analog electronics

Does anyone have experience in applying for "software copyright"? Is there a format for the design description?: Does anyone have experience in applying for "software copyright"? Is there a format for the design description?...; 蓝雨夜 Talking

PIC struct nesting MPLAB compilation error!: Please help me solve the problem. There is a statement that can be compiled in C51: struct{ any_data[5]; any_data[8]; }no1; struct{ struct part no1[2]; any_data[2]; }no2; and passed to PIC: struct{ an...; zhf6050 Microchip MCU

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components