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Datasheet> All Categories > storage> storage> NT4GC64B8HG0NF-CG
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NT4GC64B8HG0NF-CG

Description
DDR DRAM Module, 512MX64, CMOS, HALOGEN FREE AND ROHS COMPLIANT, UDIMM-240
Categorystorage    storage   
File Size708KB，23 Pages
ManufacturerNanya
Websitehttp://www.nanya.com/cn
Nanya Technology Co., Ltd. aims to become the best DRAM (dynamic random access memory) supplier. It emphasizes customer service and strengthens product R&D and manufacturing through close cooperation with partners, thereby providing customers with comprehensive products and system solutions. In the face of the growing niche DRAM market, Nanya Technology not only provides products ranging from 128Mb to 8Gb, but also continues to expand product diversification. The main application markets include digital TV, set-top box (STB), network communication, tablet computer and other smart electronic systems, automotive and industrial products. At the same time, in order to meet the needs of the rapidly growing mobile and wearable device market, Nanya Technology is more focused on the research and development and manufacturing of low-power memory products. In recent years, Nanya Technology has actively operated in the niche memory market, focusing on the research and development of low-power and customized core product lines. In terms of process progress, it has also introduced 20nm process technology and is committed to the production of DDR4 and LPDDR4 products, hoping to further enhance its overall competitiveness. Nanya Technology will also continue to strengthen its high value-added niche memory products and perfect customer service, enhance core business operating performance, ensure the rights and interests of all shareholders, and create sustainable business value for the company.
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NT4GC64B8HG0NF-CG Overview

DDR DRAM Module, 512MX64, CMOS, HALOGEN FREE AND ROHS COMPLIANT, UDIMM-240

NT4GC64B8HG0NF-CG Parametric

Parameter NameAttribute value
MakerNanya
Parts packaging codeDIMM
package instructionDIMM,
Contacts240
Reach Compliance Codeunknow
ECCN codeEAR99
access modeDUAL BANK PAGE BURST
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-XDMA-N240
JESD-609 codee4
length133.35 mm
memory density34359738368 bi
Memory IC TypeDDR DRAM MODULE
memory width64
Number of functions1
Number of ports1
Number of terminals240
word count536870912 words
character code512000000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature
organize512MX64
Package body materialUNSPECIFIED
encapsulated codeDIMM
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Maximum seat height30.5 mm
self refreshYES
Maximum supply voltage (Vsup)1.575 V
Minimum supply voltage (Vsup)1.425 V
Nominal supply voltage (Vsup)1.5 V
surface mountNO
technologyCMOS
Temperature levelOTHER
Terminal surfaceGOLD
Terminal formNO LEAD
Terminal pitch1 mm
Terminal locationDUAL

NT4GC64B8HG0NF-CG Preview

NT2GC64B88G0NF / NT4GC64B8HG0NF
2GB: 256M x 64 / 4GB: 512M x 64
PC3-10600 / PC3-12800
Unbuffered DDR3 SDRAM DIMM
Based on DDR3-1333/1600 256Mx8 SDRAM G-Die
Features
•Performance:
Speed Sort
DIMM CAS Latency
fck – Clock Freqency
tck – Clock Cycle
fDQ – DQ Burst Freqency
PC3-10600
-CG
9
667
1.5
1333
PC3-12800
-DI
11
800
1.25
1600
MHz
ns
Mbps
Unit
• 240-Pin Dual In-Line Memory Module (UDIMM)
• 256Mx64 (2GB) / 512Mx64 (4GB) DDR3 Unbuffered DIMM based
on 256Mx8 DDR3 SDRAM G-Die devices.
• Intended for 667MHz/800MHz applications
• Inputs and outputs are SSTL-15 compatible
• V
DD
= V
DDQ
= 1.5V ±0.075V
• SDRAMs have 8 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock transitions.
• Address and control signals are fully synchronous to positive
clock edge
• Nominal and Dynamic On-Die Termination support
• Programmable Operation:
- DIMM

Latency: 5, 6, 7,8,9,10,11
- Burst Type: Sequential or Interleave
- Burst Length: BC4, BL8
- Operation: Burst Read and Write
• Two different termination values (Rtt_Nom & Rtt_WR)
• 15/10/1 (row/column/rank) Addressing for 2GB
• 15/10/2 (row/column/rank) Addressing for 4GB
• Extended operating temperature rage
• Auto Self-Refresh option
• Serial Presence Detect
• Gold contacts
• SDRAMs are in 78-ball BGA Package
• RoHS compliance and Halogen free product
Description
NT2GC64B88G0NF / NT4GC64B8HG0NF are 240-Pin Double Data Rate 3 (DDR3) Synchronous DRAM Unbuffered Dual In-Line Memory
Module (UDIMM), organized as one rank of 256Mx64 (2GB) and two ranks of 512Mx64 (4GB) high-speed memory array. Modules use eight
256Mx8 (2GB) 78-ball BGA packaged devices and sixteen 256Mx8 (4GB) 78-ball BGA packaged devices. These DIMMs are manufactured
using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation
between suppliers. All NANYA DDR3 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving
footprint.
The DIMM is intended for use in applications operating of 667MHz/800MHz clock speeds and achieves high-speed data transfer rates of
1333Mbps/12800Mbps. Prior to any access operation, the device

latency and burst/length/operation type must be programmed into
the DIMM by address inputs A0-A13 (2GB) / A0-A14 (4GB) and I/O inputs BA0~BA2 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data
are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
REV 1.1
10/2011
1
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT2GC64B88G0NF / NT4GC64B8HG0NF
2GB: 256M x 64 / 4GB: 512M x 64
PC3-10600 / PC3-12800
Unbuffered DDR3 SDRAM DIMM
Ordering Information
Part Number
NT2GC64B88G0NF-CG
NT2GC64B88G0NF-DI
NT4GC64B8HG0NF-CG
NT4GC64B8HG0NF-DI
DDR3-1333
DDR3-1600
DDR3-1333
DDR3-1600
Speed
PC3-10600
667MHz (1.5ns @ CL = 9)
256Mx64
PC3-12800 800MHz (1.25ns @ CL = 11)
1.5V
PC3-10600
667MHz (1.5ns @ CL = 9)
512Mx64
PC3-12800 800MHz (1.25ns @ CL = 11)
Gold
Organization
Power
Leads
Note
Pin Description
Pin Name
CK0, CK1
, 
CKE0, CKE1



, 
A10/AP
A12/
BA0-BA2
ODT0, ODT1
SCL
SDA
Description
Clock Inputs, positive line
Clock Inputs, negative line
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Input/Auto-Precharge
Address Input/Burst Chop
SDRAM Bank Address Inputs
Active termination control lines
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Pin Name
DQ0-DQ63
DQS0-DQS8
-
DM0-DM8


V
REFDQ
, V
REFCA
V
DDSPD
SA0, SA1
Vtt
V
SS
V
DD
NC
Data strobes
Data strobes complement
Data Masks
Temperature event pin
Reset pin
Input/Output Reference
SPD and Temp sensor power
Serial Presence Detect Address Inputs
Termination voltage
Ground
Core and I/O power
No Connect
Description
Data input/output
A0-A9, A11, A13-A15 Address Inputs
REV 1.1
10/2011
2
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT2GC64B88G0NF / NT4GC64B8HG0NF
2GB: 256M x 64 / 4GB: 512M x 64
PC3-10600 / PC3-12800
Unbuffered DDR3 SDRAM DIMM
DDR3 SDRAM Pin Assignment
Pin
1
2
Front
Pin
Back
V
SS
DQ4
Pin
31
32
Front
DQ25
V
SS

DQS3
V
SS
DQ26
DQ27
V
SS
Pin
151
152
Back
V
SS
DM3,DQS12,T
DQS12
NC,

V
SS
DQ30
DQ31
V
SS
CB4,NC
CB5,NC
V
SS
DM8,DQS17,
TDQS17,NC
NC,,
,
V
SS
CB6,NC
CB7,NC
V
SS
NC(TEST)

CKE1/NC
Pin
61
62
Front
A2
V
DD
Pin
181
182
Back
A1
V
DD
Pin
91
92
Front
DQ41
V
SS

DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS

DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS

DQS7
V
SS
Pin
211
212
Back
V
SS
V
REFDQ
121
V
SS
122
3
4
5
6
7
8
9
10
11
DQ0
DQ1
V
SS
123
124
125
DQ5
V
SS
DM0,DQS9,
TDQS9
NC,

V
SS
DQ6
DQ7
V
SS
DQ12
33
34
35
36
37
38
39
40
41
153
154
155
156
157
158
63
64
65
66
67
68
69
70
71
CK1,NC
,NC
V
DD
V
DD
V
REFCA
P
AR
_I
N
,
NC
V
DD
A10/AP
BA0
183
184
185
186
187
188
189
190
191
V
DD
CK0

V
DD
,
NC
A0
V
DD
BA1
V
DD


V
DD
ODT0
A13
V
DD
,NC
V
SS
DQ36
93
94
95
96
97
98
99
100
101
DM5,
DQS14,
TDQS14
NC,
213
,

214
215
216
217
218
219
220
221
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS

126
DQS0 127
V
SS
DQ2
DQ3
V
SS
128
129
130
131
CB0,NC 159
CB1,NC 160
V
SS

DQS8
V
SS
161
12
13
14
15
16
17
18
19
20
DQ8
DQ9
V
SS

132
133
134
DQ13
V
SS
42
43
44
45
46
47
48
49
50
162
163
164
72
73
74
75
76
77
78
79
80
V
DD


V
DD
,NC
ODT1,NC
192
193
194
195
196
197
198
199
200
102
103
104
105
106
107
108
109
110
DM6,
DQS15,
TDQS15
NC,
222
,

223
224
225
226
227
228
229
230
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM1, DQS10,
TDQS10
NC,
135

V
SS
DQ14
DQ15
V
SS
DQ20
137
CB2,NC 165
CB3,NC 166
V
SS
V
TT
,NC
V
TT
,NC
CKE0
167
168
169
170
DQS1 136
V
SS
DQ10 138
DQ11 139
V
SS
140
V
DD
,NC
V
SS
V
DD
21
22
23
DQ16 141
DQ17 142
V
SS
143
DQ21
V
SS
DM2, DQS11,
TDQS11
NC,

V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
51
52
53
V
DD
BA2
171
172
A15,NC
A14
V
DD
81
82
83
DQ32
DQ33
V
SS

DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
201
202
DQ37
V
SS
111
112
DM7,
DQS16,
TDQS16
NC,
231
,

232
233
V
SS
DQ62
E
RR
_O
UT
173
,NC
V
DD
A11
A7
V
DD
A5
A4
V
DD
174
175
176
177
178
179
180
24
25
26
27
28
29
30

144
DQS2 145
V
SS
146
54
55
56
57
58
59
60
A12/
A9
V
DD
A8
A6
V
DD
A3
84
85
86
87
88
89
90
DM4,
203 DQS13, 113
TDQS13
NC,
204
,
114

205
206
207
208
209
210
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
115
116
117
118
119
120
DQ58
DQ59
V
SS
SA0
SCL
SA2
V
TT
234
235
236
237
238
239
240
DQ63
V
SS
V
DDSPD
SA1
SDA
V
SS
V
TT
DQ18 147
DQ19 148
V
SS
149
DQ24 150
Note: CK1,
,
CKE1,

and ODT1 are for 4GB modules only.
REV 1.1
10/2011
3
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT2GC64B88G0NF / NT4GC64B8HG0NF
2GB: 256M x 64 / 4GB: 512M x 64
PC3-10600 / PC3-12800
Unbuffered DDR3 SDRAM DIMM
Input/Output Functional Description
Symbol
CK0, CK1
, 
CKE0, CKE1
, 

,

,

ODT0, ODT1
DM0 – DM8
Type
Input
Input
Input
Polarity
Cross
point
Active
High
Active
Low
Active
Low
Active
High
Active
High
Function
The system clock inputs. All address and command lines are sampled on the cross point of the
rising edge of CK and falling edge of
.
A Delay Locked Loop (DLL) circuit is driven from the
clock inputs and output timing for read operations is synchronized to the input clock.
Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
Enables the associated DDR3 SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored but
previous operations continue, Rank 0 is selected by
;
Rank 1 is selected by

When sampled at the positive rising edge of CK and falling edge of
,
signals

,

,

define the operation to be executed by the SDRAM.
Asserts on-die termination for DQ, DM, DQS, and

signals if enabled via the DDR3 SDRAM
mode register.
The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask
by allowing input data to be written if it is low but blocks the write operation if it is high. In Read
mode, DM lines have no effect.
The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the
data strobe is sourced by the controller and is centered in the data window. In Read mode, the
data strobe is sourced by the DDR3 SDRAM and is sent at the leading edge of the data window.

signals are complements, and timing is relative to the cross point of respective DQS and
.
If the module is to be operated in single ended strobe mode, all

signals must be tied on
the system board to V
SS
and DDR3 SDRAM mode registers programmed appropriately.
Selects which DDR3 SDRAM internal bank of four or eight is activated.
During a Bank Activate command cycle, defines the row address when sampled at the cross point
of the rising edge of CK and falling edge of
.
During a Read or Write command cycle, defines
the column address when sampled at the cross point of the rising edge of CK and falling edge of
.
In addition to the column address, AP is used to invoke autoprecharge operation at the end of
the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the
bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command
cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is
high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then
BA0-BAn are used to define which bank to precharge.
Data Input/Output pins.
Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module.
Reference voltage for SSTL15 inputs
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor.
A resistor must be connected from the SDA bus line to V
DDSPD
on the system planar to act as a pull
up.
This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.
Address pins used to select the Serial Presence Detect and Temp sensor base address.
The

pin is reserved for use to flag critical module temperature.
This signal resets the DDR3 SDRAM
Input
Input
Input
DQS0 – DQS8

–

I/O
Cross
point
BA0, BA1, BA2
Input
-
A0 – A9
A10/AP
A11
A12/
A13-A15
Input
-
DQ0 – DQ63
V
DD
,
V
DDSPD,
V
SS
V
REFDQ,
V
REFCA
SDA
SCL
SA0 – SA2


Input
Supply
Supply
-
-
-
-
-
-
-
-
I/O
Input
Input
Output
Input
REV 1.1
10/2011
4
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT2GC64B88G0NF / NT4GC64B8HG0NF
2GB: 256M x 64 / 4GB: 512M x 64
PC3-10600 / PC3-12800
Unbuffered DDR3 SDRAM DIMM
Functional Block Diagram
[2GB
–
1 Rank, 256Mx8 DDR3 SDRAMs]


DQS0
DM0
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7

DQS

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQS4
DM4
DM
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7

DQS

D0
D4
ZQ
ZQ

DQS1
DM1
DM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7

DQS


DQS5
DM5
DM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7

DQS

D1
D5
ZQ
ZQ

DQS2
DM2
DM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7

DQS


DQS6
DM6
DM
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7

DQS

D2
D6
ZQ
ZQ

DQS3
DM3
DM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7

DQS


DQS7
DM7
DM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7

DQS

D3
D7
ZQ
ZQ
SCL
SA0
SA1
SCL
A0
A1
A2
SPD
SDA
WP
DDR3
SDRAM
CKE0, A[13:0],
, , ,
ODT0, BA[2:0],

DDR3
SDRAM
CK

V
DD
V
TT
V
DDSPD
V
DD
/V
DDQ
V
REFDQ
V
SS
V
REFCA
BA0-BA2
A0-A13


CKE0

ODT0
CK0


SPD
D0-D7
D0-D7
D0-D7
D0-D7
BA0-BA2: SDRAMs D0-D7
A0-A13: SDRAMs D0-D7
:
SDRAMs D0-D7
:
SDRAMs D0-D7
CKE: SDRAMs D0-D7
:
SDRAMs D0-D7
ODT: SDRAMs D0-D7
CK: SDRAMs D0-D7
:
SDRAMs D0-D7
:
SDRAMs D0-D7
Notes :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown.
3. For each DRAM, a unique ZQ resistor is connected to ground. The ZQ
resistor is 240Ω±1%.
4. One SPD exists per module.
REV 1.1
10/2011
5
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
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