The UT54ACTS00E is a quadruple, two-input NAND gate.
The circuit performs the Boolean functions Y = AB or Y = A
+ B in positive logic.
The device is characterized over full military temperature range
of -55C to +125C.
FUNCTION TABLE
INPUTS
A
H
L
X
B
H
X
L
OUTPUT
Y
L
H
H
LOGIC DIAGRAM
A1
B1
A2
B2
A3
B3
A4
B4
Y4
Y3
Y1
Y2
LOGIC SYMBOL
(1)
(2)
(4)
(5)
(9)
(10)
(12)
(13)
(11)
(6)
(8)
Y2
Y3
Y4
A1
B1
A2
B2
A3
B3
A4
B4
&
(3)
Y1
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
1
OPERATIONAL ENVIRONMENT
1
PARAMETER
Total Dose
SEU Threshold
2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6
108
120
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
JC
I
I
P
D2
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum power dissipation permitted @ Tc=125
o
C
LIMIT
-0.3 to 7.0
-.3 to V
DD
+.3
-65 to +150
+175
+300
15.5
10
3.2
UNITS
V
V
C
C
C
C/W
mA
W
Note:
1.Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
2. Per MIL-STD-883, method 1012.1, Section 3.4.1, P
D
= (T
j(max)
- T
c(max)
) /
jc
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
3.0 to 5.5
0 to V
DD
-55 to + 125
UNITS
V
V
C
2
DC ELECTRICAL CHARACTERISTICS
(Pre and Post-Radiation)*
(V
DD
= 5.0V
10%; V
SS
= 0V
6
, -55C < T
C
< +125C)
;
Unless otherwise noted, Tc is per the temperature range ordered
SYMBOL
V
IL1
V
IL2
V
IH1
V
IH2
I
IN
V
OL1
DESCRIPTION
Low-level input voltage
1
Low-level input voltage
1
High-level input voltage
1
High-level input voltage
1
Input leakage current
Low-level output voltage
3
CONDITION
V
DD
from 4.5V to 5.5V
V
DD
from 3.0V to 3.6V
V
DD
from 4.5V to 5.5V
V
DD
from 3.0V to 3.6V
V
IN
= V
DD
or V
SS
I
OL
= 8mA
V
DD
= 4.5V to 5.5V
V
OL2
Low-level output voltage
3
I
OL
= 6mA
V
DD
= 3.0V to 3.6V
V
OH1
High-level output voltage
3
I
OH
= -8mA
V
DD
from 4.5V to 5.5V
V
OH2
High-level output voltage
3
I
OH
= -6mA
V
DD
from 3.0V to 3.6V
I
OS1
Short-circuit output current
2 ,4
V
O
= V
DD
and V
SS
V
DD
from 4.5V to 5.5V
I
OS2
Short-circuit output current
2 ,4
V
O
= V
DD
and V
SS
V
DD
from 3.0V to 3.6V
I
OL1
Low level output current
8
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
V
DD
from 4.5V to 5.5V
I
OL2
Low level output current
8
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
V
DD
from 3.0V to 3.6V
I
OH1
High level output current
8
V
IN
= V
DD
or V
SS
V
OH
= V
DD
-0.4V
V
DD
from 4.5V to 5.5V
I
OH2
High level output current
8
V
IN
= V
DD
or V
SS
V
OH
= V
DD
-0.4V
V
DD
from 3.0V to 3.6V
P
total1
Power dissipation
2, 7
C
L
= 50pF
V
DD
= 4.5V to 5.5V
3
MIN
MAX
0.8
0.8
UNIT
V
V
V
V
0.5 V
DD
2.0
-1
1
0.4
A
V
0.4
V
0.7 V
DD
V
2.4
V
-200
200
mA
-100
100
mA
8
mA
6
mA
-8
mA
-6
mA
1
mW/
MHz
P
total2
Power dissipation
2, 7
C
L
= 50pF
V
DD
= 3.0V to 3.6V
0.5
mW/
MHz
A
I
DDQ
I
DDQ
Quiescent Supply Current
V
IN
= V
DD
or V
SS
V
DD
from 3.6V to 5.5V
10
Quiescent Supply Current Delta
For input under test
V
IN
= V
DD
- 2.1V
For all other inputs
V
IN
= V
DD
or V
SS
V
DD
= 5.5V
= 1MHz
V
DD
= 0V
= 1MHz
V
DD
= 0V
1.6
mA
C
IN
Input capacitance
5
Output capacitance
5
15
pF
C
OUT
15
pF
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25
o
C per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to V
IH
(min) and V
IL
(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density
5.0E5
amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/
MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. Power dissipation specified per switching output.
8. Parameter guaranteed by design and characterization, but is not tested.
AC ELECTRICAL CHARACTERISTICS
(Pre and Post-Radiation)*
(V
DD
= 3.0V to 5.5V; V
SS
= 0V
1
, -55C < T
C
< +125C); Unless otherwise noted, Tc is per the temperature range ordered
SYMBOL
t
PLH
PARAMETER
Input to Yn
CONDITION
C
L
= 50pF
V
DD
3.0V to 3.6V
4.5V to 5.5V
t
PHL
Input to Yn
C
L
= 50pF
3.0V to 3.6V
4.5V to 5.5V
MINIMUM
2
1
2
1
MAXIMUM
12
6
11
7
ns
UNIT
ns
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25×C per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Maximum allowable relative shift equals 50mV.
4
Packaging
1. All exposed metallized areas are gold plated over
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