INTEGRATED CIRCUITS
DATA SHEET
TDA1307
High-performance bitstream digital
filter
Preliminary specification
Supersedes data of July 1993
File under Integrated Circuits, IC01
1996 Jan 08
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
FEATURES
•
Multiple format inputs: I
2
S, Sony 16, 18 and 20-bit
•
8-sample interpolation error concealment
•
Digital mute, attenuation
−12
dB
•
Digital audio output function (biphase-mark encoded)
according to IEC 958
•
Digital silence detection (output)
•
Digital de-emphasis (selectable, FS-programmable)
•
8
×
oversampling finite impulse response (FIR) filter
•
DC-cancelling filter (selectable)
•
Peak detection (continuous) and read-out to
microprocessor
•
Fade function: sophisticated volume control
•
Selectable 3rd/4th order noise shaping
•
Selectable dither generation and automatic scaling
•
Dedicated TDA1547 1-bit output
TDA1307
•
Differential mode bitstream: complementary data
outputs available
•
Simple 3-line serial microprocessor command interface
•
Flexible system clock oscillator circuitry
•
Power-on reset
•
Standby function
•
SDIP42 package.
QUICK REFERENCE DATA
Voltages are referenced to V
SS
(ground = 0 V); all V
SS
and all V
DD
connections should be connected externally to the
same supply.
SYMBOL
V
DDC1,2,3
V
DDOSC
V
DDAR
V
DDAL
I
DDC1,2,3
I
DDOSC
I
DDAR
I
DDAL
f
XTAL
T
amb
P
tot
PARAMETER
supply voltage
(pins 21, 41 and 8)
supply voltage (pin 24)
supply voltage (pin 32)
supply voltage (pin 29)
supply current
(pins 21, 41 and 8)
supply current (pin 24)
supply current (pin 32)
supply current (pin 29)
oscillator clock frequency
operating ambient temperature
total power consumption
V
DD
= 5 V
V
DD
= 5 V
V
DD
= 5 V
V
DD
= 5 V
CONDITIONS
MIN.
4.5
4.5
4.5
4.5
−
−
−
−
−
−20
−
TYP.
5.0
5.0
5.0
5.0
75
2
2
1
−
400
MAX.
5.5
5.5
5.5
5.5
−
−
−
−
+70
−
V
V
V
V
mA
mA
mA
mA
MHz
°C
mW
UNIT
33.8688
−
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
TDA1307
SDIP42
DESCRIPTION
plastic shrink dual in-line package; 42 leads (600 mil)
VERSION
SOT270-1
1996 Jan 08
2
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
GENERAL DESCRIPTION
The TDA1307 is an advanced oversampling digital filter
employing bitstream conversion technology, which has
been designed for use in premium performance digital
audio applications. Audio data is input to the TDA1307
through its multiple-format interface. Any of the four
formats (I
2
S, Sony 16, 18 or 20-bit) are acceptable. By
using a highly accurate audio data processing structure,
including 8 times oversampling digital filtering and up to
4th order noise shaping, a high quality bitstream is
produced which, when used in the recommended
combination with the TDA1547 bitstream DAC, provides
the optimum in dynamic range and signal-to-noise
performance. With the TDA1307, a high degree of
versatility is achieved by a multitude of functional features
and their easy accessibility; error concealment functions,
TDA1307
audio peak data information and an advanced patented
digital fade function are accessible through a simple
microprocessor command interface, which also provides
access to various integrated system settings
and functions.
TDA1307 plus TDA1547 high-performance bitstream
digital filter plus DAC combination:
For many features:
•
Highly accessible structure
•
Intelligent audio data processing.
For optimum performance:
•
4th order noise shaping
•
Improvement dynamic range (113 dB)
•
Improvement signal-to-noise (115 dB).
handbook, full pagewidth
fsystem = 768fs
20-bit fs
1-bit, 192fs
L
TDA1307
TDA1547
R
8
×
oversampling FIR
filter, 20-bit
24
×
upsampling
3rd or 4th order noise shaping,
1-bit end quantization
1-bit high-performance
digital-to-analog
converter
3rd order analog
postfilter, fo = 55 kHz
Butterworth response
MGB983
Fig.1 High performance bitstream reconstruction system.
1996 Jan 08
3
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
BLOCK DIAGRAM
TDA1307
handbook, full pagewidth
WS
1
1fs AUDIO DATA INPUTS
SCK
2
SD
3
EFAB
4
TDA1307
MULTIPLE FORMAT
INPUT INTERFACE
19
RESYNC
10
ERROR CONCEALMENT,
INTERPOLATION, MUTING
DIGITAL
OUTPUT
13
5
6
12
11
36
37
DE–EMPHASIS FILTER
22
23
DIGITAL SILENCE DETECTION
DOBM
DSTB
SBCL
SBDA
DSR
DSL
TEST1
TEST2
25
VSSOSC
XTAL1
FIR HALFBAND FILTER
STAGE 1: 1fs to 2fs
38
DA
39
CL
RAB
42
MICRO–
PROCESSOR
INTERFACE
DC–CANCELLING FILTER
CRYSTAL
OSCILLATOR
XTAL2
CLOCK
GENERATION
AND
DISTRIBUTION
15
CMIC
7
CDEC
14
CLC1
17
CLC2
18
CDCC
PEAK DETECTION
POR
VDDC3
VDDC1
VDDOSC
VDDAL
VDDAR
VDDC2
20
FADE FUNCTION
VOLUME CONTROL
9
16
8
VSSC2
VSSC3
VSSAL
VSSAR
VSSC1
21
FIR HALFBAND FILTER
STAGE 2: 2fs to 4fs
30
31
40
24
FIR HALFBAND FILTER
STAGE 3: 4fs to 8fs
29
32
DITHER AND SCALING
41
3rd/4th ORDER
NOISE SHAPER
27
DOL
28
NDOL
35
CDAC
34
NDOR
33
DOR
26
MGB989
MODE
BITSTREAM DATA OUTPUTS
Fig.2 Block diagram.
1996 Jan 08
4
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
PINNING
SYMBOL
WS
SCK
SD
EFAB
SBCL
SBDA
CDEC
V
DDC3
V
SSC2
DOBM
PIN
1
2
3
4
5
6
7
8
9
10
O
TYPE, I/O
I
I
I
I
(1)
I
I
O
clock input to data interface
data input to interface
DESCRIPTION
word select input to data interface
TDA1307
error flag (active HIGH): input from decoder chip indicating unreliable data
subcode clock: a 10-bit burst clock (typ. 2.8224 MHz) input which synchronizes
the subcode data
subcode data: a 10-bit burst of data, including flags and sync bits, serially input
once per frame, clocked by burst clock input SBCL
decoder clock output: frequency division programmable by means of
pins 14 (CLC1) and 17 (CLC2) to output 192, 256, 384 or 768 times f
s
positive supply 3
ground 2
digital audio output: this output contains digital audio samples which have
received interpolation, attenuation and muting plus subcode data;
transmission is in biphase-mark code
digital silence detected (active LOW) on left channel
digital silence detected (active LOW) on right channel
DOBM standby mode enforce pin (active HIGH)
application mode programming pin for CDEC (pin 7) frequency division
clock output, provided to be used as running clock by microprocessor
(in master mode only), output 96f
s
ground 3
application mode programming pin for CDEC (pin 7) frequency division
master / slave mode selection pin
resynchronization: out-of-lock indication from data input section (active HIGH)
power-on reset (active LOW)
supply voltage 1
crystal oscillator terminal: local crystal oscillator sense forced input in slave mode
crystal oscillator output: drive output to crystal
positive supply connection to crystal oscillator circuitry
ground connection to crystal oscillator circuitry
DSL
DSR
DSTB
CLC1
CMIC
V
SSC3
CLC2
CDCC
RESYNC
POR
V
DDC1
XTAL1
XTAL2
V
DDOSC
V
SSOSC
MODE
DOL
NDOL
V
DDAL
V
SSAL
V
SSAR
V
DDAR
DOR
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
O
O
I
(2)
I
O
I
I
O
I
(2)
I
O
I
(2)
O
O
evaluation mode programming pin (active LOW); in normal operation, this pin
should be left open-circuit or connected to the positive supply
data output left channel to bitstream DAC TDA1547
complementary data output left channel to TDA1547 in double differential mode
positive supply connection to output data driving circuitry, left channel
ground connection to output data driving circuitry, left channel
ground connection to output data driving circuitry, right channel
positive supply connection to output data driving circuitry, right channel
O
data output right channel to TDA1547
1996 Jan 08
5
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