Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)
FEATURES
•
Easy application
•
16f
s
Finite-duration Impulse-Response (FIR)
filter incorporated
•
Selectable system clock (f
sys
) 256f
s
or 384f
s
•
I
2
S-bus serial input format (at f
sys
= 256f
s
) or LSB fixed
16, 18 or 20 bits serial input mode (at f
sys
= 384f
s
)
•
Slave-mode clock system
•
Cascaded 4-stage digital filter incorporating 2-stage FIR
filter, linear interpolator and sample-and-hold
•
Smoothed transitions before and after muting
(soft mute)
•
Digital de-emphasis filter for three sampling rates of
32 kHz, 44.1 kHz and 48 kHz
•
12 dB attenuation via the attenuation input control
•
Double speed mode
•
2nd order noise shaper
•
96 (f
sys
= 384f
s
) or 128 (f
sys
= 256f
s
) times oversampling
in normal speed mode
•
48 (f
sys
= 384f
s
) or 64 (f
sys
= 256f
s
) times oversampling
in double speed mode
•
Bitstream continuous calibration concept
•
Small outline SO28 package
•
Voltage output 1.5 V (RMS) at line drive level
•
Low total harmonic distortion
•
No zero crossing distortion
•
Inherently monotonic
•
No analog post filtering required
•
Superior signal-to-noise ratio
•
Wide dynamic range (18-bit)
•
Single rail supply (3.4 to 5.5 V).
GENERAL DESCRIPTION
The TDA1305T is a new generation of filter-DAC which
features a unique combination of bitstream and continuous
calibration techniques. The converter functions as a
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
TDA1305T
SO28
DESCRIPTION
plastic small outline package; 28 leads; body width 7.5 mm
TDA1305T
bitstream converter for low signals while large signals are
generated using the dynamic continuous calibration
technique, thus resulting in low power consumption, small
chip size and easy application.
The TDA1305T is a dual CMOS DAC with up-sampling
filter and noise shaper. The combination of high
oversampling up to 16f
s
, 2nd order noise shaping and
continuous calibration conversion ensures that only simple
1st order analog post filtering is required.
The TDA1305T supports the I
2
S-bus data input mode with
word lengths of up to 20 bits (at f
sys
= 256f
s
) and the LSB
fixed serial data input format with word lengths of 16, 18
and 20 bits (at f
sys
= 384f
s
). Four cascaded FIR filters
increase the oversampling rate to 16 times. A
sample-and-hold function increases the oversampling rate
to 96 times (f
sys
= 384f
s
) or 128 times (f
sys
= 256f
s
). A
2nd order noise shaper converts this oversampled data to
a bitstream for the 5-bit DACs.
The DACs are of the continuous calibration type and
incorporate a special date coding. This ensures an
extremely high signal-to-noise ratio, superior dynamic
range and immunity to process variation and component
ageing.
Two on-board operational amplifiers convert the
digital-to-analog current to an output voltage. Externally
connected capacitors perform the required 1st order
filtering so that no further post filtering is required.
The unique combination of bitstream and continuous
calibration techniques, together with a high degree of
analog and digital integration, results in a single filter-DAC
with 18-bit dynamic range, high linearity and simple low
cost application.
VERSION
SOT136-1
1995 Dec 08
2
Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)
PINNING
SYMBOL
V
DDA
V
SSA
TEST1
PIN
1
2
3
DESCRIPTION
analog supply voltage
analog ground
test input; pin should be connected
to ground (internal pull-down
resistor)
bit clock input
word select input
data input
clock selection 1 input
clock selection 2 input
digital ground
digital supply voltage
test input; pin should be connected
to ground (internal pull-down
resistor)
system clock input
not connected (this pin should be left
open-circuit)
not connected (this pin should be left
open-circuit)
digital ground
system clock output
de-emphasis on/off; f
DEEM
32 kHz,
44 kHz and 48 kHz
de-emphasis on/off; f
DEEM
32 kHz,
44 kHz and 48 kHz
mute input (active LOW)
double-speed mode input
(active LOW)
12 dB attenuation input
(active LOW)
left channel output
capacitor for left channel 1st order
filter function should be connected
between pins 22 and 23
capacitor for right channel 1st order
filter function should be connected
between pins 25 and 24
right channel output
internal reference voltage for output
channels (0.5V
DD
)
operational amplifier ground
operational amplifier supply voltage
5
TDA1305T
BCK
WS
DATA
CLKS1
CLKS2
V
SSD
V
DDD
TEST2
4
5
6
7
8
9
10
11
SYSCLKI
n.c.
n.c.
V
SSD
SYSCLKO
DEEM1
DEEM2
MUSB
DSMB
ATSB
VOL
FILTCL
12
13
14
15
16
17
18
19
20
21
22
23
FILTCR
24
VOR
V
ref
V
SSO
V
DDO
1995 Dec 08
25
26
27
28
Fig.2 Pin configuration.
Microcontroller MCU
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