2-WIRE SERIAL TEMPERATURE
SENSOR AND THERMAL MONITOR
PRELIMINARY INFORMATION
TCN75
TCN75
2-WIRE SERIAL TEMPERATURE SENSOR AND THERMAL MONITOR
FEATURES
s
s
s
s
s
s
s
s
s
s
Solid State Temperature Sensing; 2
°
C Accuracy (Typ.)
Operates from – 55
°
C to +125
°
C
Operating Range ..................................... 2.7V - 5.5V
Programmable Trip Point and Hysteresis with
Power-up Defaults
Standard 2-Wire Serial Interface
Thermal Event Alarm Output Functions as
Interrupt or Comparator / Thermostat Output
Up to 8 TCN75's May Share the Same Bus
Shutdown Mode for Low Standby Power
Consumption
Low Power ......................... 250
µ
A (Typ.) Operating
1
µ
A (Typ.) Shutdown Mode
8-Pin Plastic DIP, SOIC, and MSOP Packaging
perature exceeds a user-programmed setpoint. Hysteresis
is also programmable. The INT/CMPTR output is program-
mable as either a simple comparator for thermostat opera-
tion or as a temperature event interrupt. Communication
with the TCN75 is accomplished via a two-wire bus that is
compatible with industry standard protocols. This permits
reading the current temperature, programming the setpoint
and hysteresis, and configuring the device.
The TCN75 powers up in Comparator Mode with a
default setpoint of 80°C with 5°C hysteresis. Defaults allow
independent operation as a stand-alone thermostat. A shut-
down command may be sent via the 2-wire bus to activate
the low-power standby mode. Address selection inputs
allow up to eight TCN75's to share the same 2-wire bus for
multi-zone monitoring.
All registers can be read by the host and the INT/
CMPTR output's polarity is user programmable. Both polled
and interrupt driven systems are easily accommodated.
Small physical size, low installed cost, and ease of use make
the TCN75 an ideal choice for implementing sophisticated
system management schemes.
TYPICAL APPLICATIONS
s
s
s
s
Thermal Protection for High Performance CPU's
Solid-State Thermometer
Fire/Heat Alarms
Thermal Management in Electronic Systems:
Computers
Telecom Racks
Power Supplies / UPS* / Amplifiers
Copiers / Office Electronics
Consumer Electronics
Process Control
ORDERING INFORMATION
Part No.
TCN75-3.3MOA
TCN75-5.0MOA
TCN75-3.3MPA
TCN75-5.0MPA
TCN75-3.3MUA
TCN75-5.0MUA
s
s
s
Supply
Voltage (V) Package
3.3
5.0
3.3
5.0
3.3
5.0
8-Pin SOIC
8-Pin SOIC
8-Pin PDIP
8-Pin PDIP
8-MSOP
8-MSOP
Junction
Temp. Range
– 55°C to +125°C
– 55°C to +125°C
– 55°C to +125°C
– 55°C to +125°C
– 55°C to +125°C
– 55°C to +125°C
GENERAL DESCRIPTION
The TCN75 is a serially programmable temperature
sensor that notifies the host controller when ambient tem-
FUNCTIONAL BLOCK DIAGRAM
INT/CMPTR
9 Bit
∆Σ
A/D
Converter
Temp
Sensor
PIN CONFIGURATIONS
8-Pin Plastic DIP
SDA
Control
Logic
1
2
3
4
8
7
V
DD
A0
A1
A2
SDA 1
SCL 2
SCL
INT/CMPTR
TCN75MPA
6
5
8-Pin MSOP
8
7
TCN75MUA
6
5
V
DD
A0
A1
A2
V
DD
Register Set
Configuration
Temperature
T
SET
T
HYST
GND
8-Pin SOIC
SDA
SCL
A
0
A
1
A
2
Two Wire
Serial Port
Interface
INT/CMPTR 3
8
7
V
DD
A0
A1
A2
GND 4
SDA
SCL
TCN75
1
2
3
4
TCN75MOA
INT/CMPTR
GND
6
5
TCN75-04 6/16/97
1
TelCom Semiconductor reserves the right to make changes in the circuitry and specifications of its devices.
PRELIMINARY INFORMATION
2-WIRE SERIAL TEMPERATURE
SENSOR AND THERMAL MONITOR
TCN75
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (V
DD
) .................................................6.0V
ESD Susceptibility (Note 2) ..................................... (TBD)
Voltage on Any Pin ............. (GND – 0.3V) to (V
DD
+ 0.3V)
Operating Temperature Range (T
J
) ...... – 55°C to +125°C
Storage Temperature Range (T
STG
) ..... – 65°C to +150°C
Lead Temperature (Soldering, 10 sec) ................. +300°C
Thermal Resistance (Junction to Ambient)
8-Pin DIP ...................................................... 110°C/W
8-Pin SOIC .................................................. 170°C/W
8-Pin MSOP ................................................ 250°C//W
*This is a stress rating only and functional operation of this device at these
or any other conditions above those indicated in the operations sections of
this specification is not implied.
ELECTRICAL CHARACTERISTICS:
V
DD
= 2.7V – 5.5V, – 55°C
≤
(T
A
= T
J
)
≤
125°C, unless otherwise noted.
Symbol
V
DD
I
DD
I
DD1
Parameter
Power Supply Voltage
Operating Current
Standby Supply Current
Test Conditions
Min
2.7
—
—
—
Typ
—
0.250
—
1
Max
5.5
—
1.0
—
Unit
V
mA
µA
Power Supply
Serial Port Inactive
(T
A
= T
J
= 25°C)
Serial Port Active
Shutdown Mode, Serial Port Inactive
(T
A
= T
J
= 25°C)
INT/CMPTR Output
I
OL
t
TRIP
V
OL
∆T
Sink Current: INT/CMPTR, SDA
Outputs
INT/CMPTR Response Time
Output Low Voltage
Temperature Accuracy (Note 2)
Note 1
User Programmable
I
OL
= 4.0mA
– 55°C
≤
T
A
≤
+125°C
V
DD
= 3.3V : TCN75-3.3MOA,
TCN75-3.3MPA, TCN75-3.3MUA
V
DD
= 5.0V: TCN75-5.0MOA,
TCN75-5.0MPA, TCN75-5.0 MUA
25°C
≤
T
A
≤
100°C
Power Up
Power Up
—
1
—
—
1
—
—
±3
4
6
0.8
—
mA
t
CONV
V
°C
Temp-to-Bits Converter
t
CONV
T
SET(PU)
T
HYST(PU)
V
IH
V
IL
V
OL
C
IN
I
LEAK
I
OL(SDA)
Conversion Time
TEMP Default Value
T
HYST
Default Value
Logic Input High
Logic Input Low
Logic Output Low
Input Capacitance SDA, SCL
I/O Leakage
SDA Output Low Current
—
—
—
—
V
DD
x 0.7
—
—
—
—
—
±0.5
100
80
75
—
—
—
15
±100
—
±2
—
—
—
—
V
DD
x 0.3
0.4
—
—
6
°C
msec
°C
°C
V
V
V
pF
pA
mA
2-Wire Serial Bus Interface
I
OL
= 3mA
(T
A
= T
J
= 25°C)
SERIAL PORT TIMING:
2.7V
≤
V
DD
≤
5.5V; – 55°C
≤
(T
A
= T
J
)
≤
125°C, C
L
= 80pf, unless otherwise noted.
Symbol
f
SC
t
LOW
t
HIGH
t
R
t
F
t
SU(START)
Parameter
Serial Port Frequency
Low Clock Period
High Clock Period
SCL and SDA Rise Time
SCL and SDA Fall Time
Start Condition Setup Time
(for repeated Start Condition)
Test Conditions
Min
0
1250
1250
—
—
1250
Typ
100
—
—
—
—
—
Max
400
—
—
250
250
—
Unit
kHz
nsec
nsec
nsec
nsec
nsec
TCN75-04 6/16/97
2
2-WIRE SERIAL TEMPERATURE
SENSOR AND THERMAL MONITOR
PRELIMINARY INFORMATION
TCN75
SERIAL PORT TIMING
(Cont.):
2.7V
≤
V
DD
≤
5.5V; – 55°C
≤
(T
A
= T
J
)
≤
125°C, C
L
= 80pf, unless otherwise
noted.
Symbol
t
H(START)
t
DSU
t
DH
t
SU(STOP)
t
IDLE
Parameter
Start Condition Hold Time
Data in Setup Time to SCL High
Data in Hold Time after SCL Low
Stop Condition Setup Time
Bus Free Time Prior to New
Transition
Test Conditions
Min
1250
100
0
1250
1250
Typ
—
—
—
—
—
Max
—
—
—
—
—
Unit
nsec
nsec
nsec
nsec
nsec
NOTES:
1. Output current should be minimized for best temperature accuracy. Power dissipation within the TCN75 will cause self-heating and
temperature drift. At maximum rated output current and saturation voltage, 4mA and 0.8V, respectively, the error amounts to 0.352°C for the
PDIP, and 0.544°C for the SOIC.
2. All part types of the TCN75 will operate properly over the wider power supply range of 2.7V to 5.5V. Each part type is tested and specified
for rated accuracy at its nominal supply voltage. As V
DD
varies from the nominal value, accuracy will degrade 1°C/V of V
DD
change.
3. Human body model, 100pF discharged through a 1.5k resistor, machine model, 200pF discharged directly into each pin.
PIN DESCRIPTION
Pin Number
1
2
3
4
5
6
7
8
Symbol
SDA
SCL
INT/CMPTR
GND
A
2
A
1
A
0
V
DD
Description
Bidirectional Serial Data.
Serial Data Clock Input.
Interrupt or Comparator Output.
System Ground.
Address Select Pin (MSB).
Address Select Pin.
Address Select Pin (LSB).
Power Supply Input.
DETAILED DESCRIPTION
A typical TCN75 hardware connection is shown in
Figure 1.
Serial Data (SDA)
Bidirectional. Serial data is transferred in both directions
using this pin.
Serial Clock (SCL)
Input. Clocks data into and out of the TCN75.
INT/CMPTR
Open Collector, Programmable Polarity. In Comparator
Mode, unconditionally driven active any time temperature
exceeds the value programmed into the T
SET
register. INT/
CMPTR will become inactive when temperature subse-
quently falls below the T
HYST
setting. (See
Register Set and
Programmer's Model.)
In Interrupt Mode, INT/CMPTR is
also made active by TEMP exceeding T
SET
; it is uncondition-
ally reset to its inactive state by reading any register via the
2-wire bus. If and when temperature falls below T
HYST
, INT/
CMPTR is again driven active. Reading any register will
clear the T
HYST
interrupt. In Interrupt Mode, the INT/CMPTR
TCN75-04 6/16/97
output is unconditionally reset upon entering Shutdown
Mode. If programmed as an active-low output, it can be
wire-ORed with any number of other open collector devices.
Most systems will require a pull-up resistor for this configu-
ration.
Note that current sourced from the pull-up resistor
causes power dissipation and may cause internal heating of
the TCN75. To avoid affecting the accuracy of ambient
temperature readings, the pull-up resistor should be made
as large as possible. INT/CMPTR's output polarity may be
programmed by writing to the INT/CMPTR POLARITY bit in
the CONFIG register. The default is active low.
Address (A2, A1, A0)
Inputs. Sets the three least significant bits of the TCN75
8-bit address. A match between the TCN75's address and
the address specified in the serial bit stream must be made
to initiate communication with the TCN75. Many protocol-
compatible devices with other addresses may share the
same 2-wire bus.
Slave Address
The four most significant bits of the Address Byte (A6,
A5, A4, A3) are fixed to 1001[B]. The states of A2, A1 and
3
PRELIMINARY INFORMATION
2-WIRE SERIAL TEMPERATURE
SENSOR AND THERMAL MONITOR
TCN75
A0 in the serial bit stream must match the states of the A2,
A1 and A0 address inputs for the TCN75 to respond with an
Acknowledge (indicating the TCN75 is on the bus and ready
to accept data). The Slave Address is represented by:
TCN75 Slave Address
1
MSB
0
0
1
A2
A1
A0
LSB
Serial Port Operation
The Serial Clock input (SCL) and bidirectional data port
(SDA) form a 2-wire bidirectional serial port for programming
and interrogating the TCN75. The following conventions are
used in this bus scheme:
TCN75 Serial Bus Conventions
Term
Transmitter
Receiver
Master
Explanation
The device sending data to the bus.
The device receiving data from the bus.
The device which controls the bus: initiating
transfers (START), generating the clock, and
terminating transfers (STOP).
The device addressed by the master.
A unique condition signaling the beginning of a
transfer indicated by SDA falling (High-Low) while
SCL is high.
A unique condition signaling the end of a transfer
indicated by SDA rising (Low - High) while SCL is
high.
A Receiver acknowledges the receipt of each
byte with this unique condition. The Receiver
drives SDA low during SCL high of the ACK
clock-pulse. The Master provides the clock pulse
for the ACK cycle.
When the bus is idle, both SDA & SCL will
remain high.
The state of SDA must remain stable during the
High period of SCL in order for a data bit to be
considered valid. SDA only changes state while
SCL is low during normal data transfers. (See
Start and Stop conditions)
Comparator/Interrupt Modes
INT/CMPTR behaves differently depending on whether
the TCN75 is in Comparator Mode or Interrupt Mode.
Comparator Mode is designed for simple thermostatic op-
eration. INT/CMPTR will go active anytime TEMP exceeds
T
SET
. When in Comparator Mode, INT/CMPTR will remain
active until TEMP falls below T
HYST
, whereupon it will reset
to its inactive state. The state of INT/CMPTR is maintained
in shutdown mode when the TCN75 is in comparator mode.
In Interrupt Mode, INT/CMPTR will remain active indefi-
nitely, even if TEMP falls below T
HYST
, until any register is
read via the 2-wire bus. Interrupt Mode is better suited to
interrupt driven microprocessor-based systems. The INT/
CMPTR output may be wire-OR'ed with other interrupt
sources in such systems. Note that a pull-up resistor is
necessary on this pin since it is an open-drain output.
Entering Shutdown Mode will unconditionally reset INT/
CMPTR when in Interrupt Mode.
Slave
Start
Stop
ACK
NOT Busy
Data Valid
SHUTDOWN MODE
When the appropriate bit is set in the configuration
register (CONFIG) the TCN75 enters its low-power shut-
down mode (I
DD
= 1µA, typical) and the temperature-to-
digital conversion process is halted. The TCN75's bus
interface remains active and TEMP, T
SET
, and T
HYST
may be
read from and written to. Transitions on SDA or SCL due to
external bus activity may increase the standby power con-
sumption. If the TCN75 is in Interrupt Mode, the state of INT/
CMPTR will be RESET upon entering shutdown mode.
Fault Queue
To lessen the probability of spurious activation of INT/
CMPTR the TCN75 may be programmed to filter out tran-
sient events. This is done by programming the desired value
into the Fault Queue. Logic inside the TCN75 will prevent the
device from triggering INT/CMPTR unless the programmed
number of sequential temperature-to-digital conversions
yield the same qualitative result. In other words, the value
reported in TEMP must remain above T
SET
or below T
HYST
for the consecutive number of cycles programmed in the
Fault Queue. Up to a six-cycle "filter" may be selected. See
Register Set and Programmer's Model.
TCN75-04 6/16/97
All transfers take place under control of a host, usually
a CPU or microcontroller, acting as the Master, which
provides the clock signal for all transfers. The TCN75
always
operates as a Slave. This serial protocol is illustrated in
Figure 2. All data transfers have two phases; and all bytes
are transferred MSB first. Accesses are initiated by a start
condition (START), followed by a device address byte and
one or more data bytes. The device address byte includes
a Read/Write selection bit. Each access must be terminated
by a Stop Condition (STOP). A convention called
Acknowl-
edge
(ACK) confirms receipt of each byte. Note that SDA
can change only during periods when SCL is LOW (SDA
changes while SCL is HIGH are reserved for Start and Stop
Conditions).
Start Condition (START)
The TCN75 continuously monitors the SDA and SCL
lines for a start condition (a HIGH to LOW transition of SDA
while SCL is HIGH), and will not respond until this condition
is met.
4
2-WIRE SERIAL TEMPERATURE
SENSOR AND THERMAL MONITOR
PRELIMINARY INFORMATION
TCN75
Address Byte
Immediately following the Start Condition, the host must
next transmit the address byte to the TCN75. The four most
significant bits of the Address Byte (A6, A5, A4, A3) are fixed
to 1001(B). The states of A2, A1 and A0 in the serial bit
stream must match the states of the A2, A1 and A0 address
inputs for the TCN75 to respond with an Acknowledge
(indicating the TCN75 is on the bus and ready to accept
data). The eighth bit in the Address Byte is a Read-Write Bit.
This bit is a 1 for a read operation or 0 for a write operation.
Acknowledge (ACK)
Acknowledge (ACK) provides a positive handshake
between the host and the TCN75. The host releases SDA
after transmitting eight bits then generates a ninth clock
cycle to allow the TCN75 to pull the SDA line LOW to
acknowledge that it successfully received the previous eight
bits of data or address.
Data Byte
After a successful ACK of the address byte, the host
must next transmit the data byte to be written or clock out the
data to be read. (See the appropriate timing diagrams.) ACK
will be generated after a successful write of a data byte into
the TCN75.
Stop Condition (STOP)
Communications must be terminated by a stop condi-
tion (a LOW to HIGH transition of SDA while SCL is HIGH).
The Stop Condition must be communicated by the transmit-
ter to the TCN75.
Power Supply
To minimize temperature measurement error, the
TCN75VO_-3 is factory calibrated at a supply voltage of
3.3V
±5V
and the TCN75CO_-5 is factory calibrated at a
supply voltage of 5V
±5%.
Either device is fully operational
ERROR (°0)
over the power supply voltage range of 2.7V to 5.5V, but
with a lower measurement accuracy. Figure 2 shows the
worst case temperature measurement error for the
TCN75CO_-3 operated at a power supply voltage of 5V
±
10%. Figure 3 shows the worst case temperature measure-
ment error for the TCN75CO_-3 operated at a power supply
voltage of 3.3V
±10%.
±5
±4
ERROR (°0)
±3
±2
±1
20
35
50
65
80
95
110
125
TCN75 Case Temeprature (°C)
Figure 2. TCN75CO_-3 Measurement Error at V
DD
= 5V
±
10%
±5
±4
±3
±2
±1
+V
DD
(3V to 5.5V)
C
Bypass
8
A
0
Address
(Set as Desired) A
1
A
2
7
6
5
TCN75
I
2
C Interface SDA
SCL
1
2
4
0.1µF Recommended
Unless Device is Mounted
Close to CPU
20
35
50
65
80
95
110
125
TCN75 Case Temeprature (°C)
Figure 3. TCN75CO_-5 Measurement Error at V
DD
= 3.3V
±
10%
3
TO PROCESSOR
INT/CMPTR
Figure 1. Typical Application
TCN75-04 6/16/97
5
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