V58C2128404SBI7 datasheet, PDF

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V58C2128404SBI7: DescriptionDDR DRAM, 32MX4, 0.75ns, CMOS, PDSO66, 0.400 X 0.875 INCH, LEAD FREE, PLASTIC, MS-024FC, TSOP2-66; Categorystorage storage; File Size977KB，62 Pages; ManufacturerProMOS Technologies Inc; Environmental Compliance

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V58C2128404SBI7 Overview

DDR DRAM, 32MX4, 0.75ns, CMOS, PDSO66, 0.400 X 0.875 INCH, LEAD FREE, PLASTIC, MS-024FC, TSOP2-66

V58C2128404SBI7 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	ProMOS Technologies Inc
Parts packaging code	TSSOP2
package instruction	0.400 X 0.875 INCH, LEAD FREE, PLASTIC, MS-024FC, TSOP2-66
Contacts	66
Reach Compliance Code	compli
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	0.75 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	143 MHz
I/O type	COMMON
interleaved burst length	2,4,8
JESD-30 code	R-PDSO-G66
length	22.22 mm
memory density	134217728 bi
Memory IC Type	DDR DRAM
memory width	4
Number of functions	1
Number of ports	1
Number of terminals	66
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32MX4
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSSOP66,.46
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	4096
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	2,4,8
Maximum standby current	0.01 A
Maximum slew rate	0.3 mA
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10.16 mm

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V58C2128(804/404/164)SB

HIGH PERFORMANCE 128 Mbit DDR SDRAM

4 BANKS X 4Mbit X 8 (804)

4 BANKS X 2Mbit X 16 (164)

4 BANKS X 8Mbit X 4 (404)

DDR400

Clock Cycle Time (t

CK2

)

Clock Cycle Time (t

CK2.5

)

Clock Cycle Time (t

CK3

)

System Frequency (f

CK max

)

7.5 ns

5ns

200 MHz

DDR400

7.5 ns

6ns

5ns

200 MHz

DDR333

7.5 ns

6 ns

166 MHz

DDR266

7.5ns

7ns

143 MHz

Features

■

High speed data transfer rates with system frequency

up to 200 MHz

■

Data Mask for Write Control

■

Four Banks controlled by BA0 & BA1

■

Programmable CAS Latency: 2, 2.5, 3

■

Programmable Wrap Sequence: Sequential

or Interleave

■

Programmable Burst Length:

2, 4, 8 for Sequential Type

2, 4, 8 for Interleave Type

■

Automatic and Controlled Precharge Command

■

Power Down Mode

■

Auto Refresh and Self Refresh

■

Refresh Interval: 4096 cycles/64 ms

■

Available in 66-pin 400 mil TSOP or 60 Ball FBGA

■

SSTL-2 Compatible I/Os

■

Double Data Rate (DDR)

■

Bidirectional Data Strobe (DQS) for input and output

data, active on both edges

■

On-Chip DLL aligns DQ and DQs transitions with CK

transitions

■

Differential clock inputs CK and CK

■

Power Supply 2.5V ± 0.2V

■

Power Supply 2.6V ± 0.1V for DDR400

*Note: (-5B) Supports PC3200 module with 2.5-3-3 timing

(-5) Supports PC3200 module with 3-3-3 timing

(-6) Supports PC2700 module with 2.5-3-3 timing

(-7) Supports PC2100 module with 2-2-2 timing

Description

The V58C2128(804/404/164)SB is a four bank DDR

DRAM organized as 4 banks x 4Mbit x 8 (804), 4 banks x

2Mbit x 16 (164), or 4 banks x 8Mbit x 4 (404). The

V58C2128(804/404/164)SB achieves high speed data

transfer rates by employing a chip architecture that

prefetches multiple bits and then synchronizes the output

data to a system clock.

All of the control, address, circuits are synchronized

with the positive edge of an externally supplied clock. I/O

transactions are occurring on both edges of DQS.

Operating the four memory banks in an interleaved

fashion allows random access operation to occur at a

higher rate than is possible with standard DRAMs. A se-

quential and gapless data rate is possible depending on

burst length, CAS latency and speed grade of the device.

Device Usage Chart

Operating

Temperature

Range

0°C to 70°C

Package Outline

JEDEC 66 TSOP II

60 FBGA

•

CK Cycle Time (ns)

-5B

•

Power

-7

•

-5

•

-6

•

Std.

•

Temperature

Mark

Blank

V58C2128(804/404/164)SB Rev.1.1 March 2004

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Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

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