V58C2256(804/404/164)SG
HIGH PERFORMANCE 256 Mbit DDR SDRAM
4 BANKS X 8Mbit X 8 (804)
4 BANKS X 4Mbit X 16 (164)
4 BANKS X 16Mbit X 4 (404)
4
DDR500
Clock Cycle Time (t
CK2
)
Clock Cycle Time (t
CK2.5
)
Clock Cycle Time (t
CK3
)
System Frequency (f
CK max
)
5ns
5ns
4ns
250 MHz
45
DDR440
5ns
5ns
4.5ns
220 MHz
5D
DDR400
5ns
5ns
5ns
200 MHz
5B
DDR400
7.5ns
5ns
5ns
200 MHz
5
DDR400
7.5ns
6ns
5ns
200 MHz
6
DDR333
7.5ns
6ns
6ns
166 MHz
7
DDR266
7.5ns
7ns
7ns
143 MHz
Features
■
High speed data transfer rates with system frequency
up to 250 MHz
■
Data Mask for Write Control
■
Four Banks controlled by BA0 & BA1
■
Programmable CAS Latency: 2, 2.5, 3
■
Programmable Wrap Sequence: Sequential
or Interleave
■
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
■
Automatic and Controlled Precharge Command
■
Power Down Mode
■
Auto Refresh and Self Refresh
■
Refresh Interval: 8192 cycles/64 ms
■
Available in 66-pin 400 mil TSOP or 60 Ball FBGA
■
SSTL-2 Compatible I/Os
■
Double Data Rate (DDR)
■
Bidirectional Data Strobe (DQS) for input and output
data, active on both edges
■
On-Chip DLL aligns DQ and DQs transitions with CK
transitions
■
Differential clock inputs CK and CK
■
Power Supply 2.5V ± 0.2V for all products
■
tRAS lockout supported
■
Concurrent auto precharge option is supported
Description
The V58C2256(804/404/164)SG is a four bank DDR
DRAM organized as 4 banks x 8Mbit x 8 (804), 4 banks x
4Mbit x 16 (164), or 4 banks x 16Mbit x 4 (404). The
V58C2256(804/404/164)SG achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output
data to a system clock.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock. I/O
transactions are occurring on both edges of DQS.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A se-
quential and gapless data rate is possible depending on
burst length, CAS latency and speed grade of the device.
Note:
(-4) Supports PC4000 module with 3-3-3 timing
(-45) Supports PC3600 module with 3-3-3 timing
(-5D) Supports PC3200 module with 2-3-3 timing
(-5B) Supports PC3200 module with 2.5-3-3 timing
(-5) Supports PC3200 module with 3-3-3 timing
(-6) Supports PC2700 module with 2.5-3-3 timing
(-7) Supports PC2100 module with 2-2-2 timing
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
JEDEC 66 TSOP II
60 FBGA
•
CK Cycle Time (ns)
-4
•
Power
-6
•
-45
•
-5D
•
-5B
•
-5
•
-7
•
Std.
•
L
•
Temperature
Mark
Blank
V58C2256(804/404/164)SG Rev.1.0 August 2008
1
ProMOS TECHNOLOGIES
Block Diagram
V58C2256(804/404/164)SG
64M x 4
Column Addresses
A0 - A9, A11, AP, BA0, BA1
Row Addresses
A0 - A12, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank 1
Row decoder
Memory array
Bank 2
Row decoder
Memory array
Bank 3
Bank 0
8192 x 1024
x8
8192 x 1024
x8
Column decoder
Sense amplifier & I(O) bus
8192 x 1024
x8
Column decoder
Sense amplifier & I(O) bus
8192 x 1024
x8
Input buffer
Output buffer
Control logic & timing generator
DQ
0
-DQ
3
CKE
RAS
CAS
WE
CK, CK
DLL
Strobe
Gen.
Data Strobe
DM
CK
CK
CS
DQS
V58C2256(804/404/164)SG Rev. 1.0 August 2008
5
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
