D M E L
Features
•
•
•
•
•
•
•
•
High Performance Phase Lock Loop Clock Distribution
Meets PC100/PC133 Registered DIMM Requirements
Spread Spectrum Clock Compatible for EMI Reduction
On-Chip Series Inductance at Each Clock Output for
Low Noise and EMI Reduction
Distributes One Clock Input to Two Banks of Clock Out-
puts
- Two Output Enables (1G, 2G)
Low Cycle to Cycle Jitter of ±100ps maximum
Standard Operating Conditions
- V
CC
3.3V ± 10%
- 0°C to +70°C
24 Lead TSSOP Package
Pin and Function Compatible with 2509, 509, and W232
clock distribution circuits
DM2509
Phase Lock Loop Clock Driver with
9-Clock Outputs
Description
The DM2509 features a low-skew, low-jitter, phase-lock loop
(PLL) clock driver for SDRAM DIMMs and other applications
requiring precise distribution of high frequency clocks. By
connecting the feedback FBIN input to FBOUT output, the
propagation delay from the CLKIN input to any clock output
will be nearly zero. This zero-delay feature allows the CLKIN
input clock to be distributed to two banks of clock outputs with
separate output controls.
The DM2509 is designed to meet the PC100 and PC133
SDRAM Registered DIMM requirments for heavy load
applications. For test purposes, the PLL can be bypassed by
strapping AV
CC
to ground.
The DM2509 has the same pinout as industry standard 2509,
509, and W232 clock distribution circuits. The DM2509 has
enhanced rise and fall times, reduced over/under-shoot, and
improved cycle to cycle jitter performance.The DM2509 has
on-chip inductance on all clock outputs 1Y(0:4), 2Y(0:3) as
well as an internal loop filter to eliminate the need for external
components. These features save board space and provide
superior performance.
Logic Diagram
Copyright © 2000 DMEL Incorporated
VIB™ is a trademark of DMEL Incorporated
PRELIMINARY
1
DM2509
Truth Table
INPUTS
1G
X
L
L
H
H
Preliminary
Pin Configuration
OUTPUTS
CLK
L
H
H
H
H
2G
X
L
H
L
H
1Y
(0:4)
L
L
L
H
H
2Y
(0:3)
L
L
H
L
H
FBOUT
L
H
H
H
H
Pin Functions
Pin Name
CLKIN
FBIN
1G
2G
FBOUT
1Y(0:4)
2Y(0:3)
Pin No.
24
13
11
14
12
3,4,5,8,9
15,16,17,
20,21
23
1
2,10,14,2
2
6,7,18,19
Type
I
I
I
I
O
O
O
Description
Reference Clock. CLKIN allows spread spectrum of 0.5% underspread.
Feedback In. FBIN provides the feedback signal to the internal PLL. Can be exter-
nally loaded to provide adjustable delay.
Output Bank Enable. When 1G is LOW, outputs 1Y[0:4] are disabled to a logic low
state. When 1G is HIGH, all outputs 1Y[0:4] are enabled.
Output Bank Enable. When 2G is Low, outputs 2Y[0:3] are disabled to a logic low
state. When 2G is HIGH, all outputs 2y[0:3] are enabled
Feedback Out. FBOUT is dedicated for external feedback. All outputs have an
internal series inductance.
Clock Out. These outputs provide low-skew copies of CLKIN. Outputs Bank
1Y(0:4) is enabled via the 1G input. All outputs have an internal series inductance.
Clock Out. These outputs provide low-skew copies of CLKIN. Outputs Bank
2Y(0:3) is enabled via the 2G input. All outputs have an internal series inductance.
Analog Power Supply. AV
CC
can be also used to bypass the PLL for test purpose.
When AV
CC
is strapped to ground, PLL is bypassed and CLKIN is buffered directly
to the device outputs.
Analog Ground. AGND provides the ground reference for the analog circuitry.
Power Supply
Ground
AV
CC
AGND
VCC
GND
Power
Ground
Power
Ground
D M E L
2
DM2509
Maximum Ratings
Supply Voltage, AV
CC
Supply Voltage, V
CC
, AV
CC
Input Voltages, V
I
Output Voltage, V
O
Input Current, V
I
< 0
Continuous Output Current
Continuous Current, V
CC
or GND
Max Power Dissipation (Note 1)
Storage Temperature
AV
CC
£ V
CC
+ 0.7V
-0.5V to 7.0V
-0.5V to V
CC
+0.5V
-0.5V to V
CC
+0.5V
-50mA
±100mA
±100mA
0.6W
-65° to +150°C
Preliminary
Note:
Stress greater than those listed in Maximum Ratings may
cause permanent damage to the device. Maximum Ratings
are stress ratings only and any operation of the device at
these or any other conditions other than those listed in the
Recommended Operating Conditions section of this specifi-
cation is not recommended or implied. Exposure to the Maxi-
mum Ratings for extended periods may affect reliability.
Notes:
1. At TA £ 55°C, still air
Recommended Operating Conditions
Symbol
AV
CC
, V
CC
V
IH
V
IL
V
I
T
A
Parameter
Analog Supply Voltage, Supply Voltage
High level input voltage
Low level input voltage
Input Voltage
Operating free-air temperature
Min.
3.0
2.0
Max.
3.6
Units
V
0.8
V
CC
70
°C
0
0
DC Electrical Characteristics
(Over Operating Range 3.0V
≤
V
CC
< 3.6V, 0°C
≤
T
A
< +70°C)
Symbol
I
VCC
I
VACC
C
I
C
O
V
OH
Output High Voltage
Parameter
Supply Current
Analog Supply Current
Input Capacitance
Output Capacitance
Conditions
V
I
= V
CC
or GND; I
O
= 0, V
CC
= 3.6V,
f = 100MHz
V
I
= V
CC
or GND; I
O
= 0, V
CC
= 3.6V,
f = 100MHz
V
I
= V
CC
or GND, V
CC
= 3.3V
V
O
= V
CC
or GND, V
CC
= 3.3V
V
CC
= 3.0V to 3.6V, I
OH
= -100µA
V
CC
= 3.0V, I
OH
= -12mA
V
CC
= 3.6V, I
OH
= -16mA
V
CC
= 3.0V to 3.6V, I
OH
= 100µA
V
CC
= 3.0V, I
OL
= 12mA
V
CC
= 3.6V, IOL = 16mA
Min.
Typ.
Max.
200
Units
mA
mA
4
6
V
CC
-0.2
2.4
2.4
0.2
0.4
0.8
pF
V
V
OL
Output Low Voltage
AC Electrical Requirements
(Over Operating Range 3.0V
≤
V
CC
< 3.6V, 0°C
≤
T
A
< +70°C)
Symbol
Fclock
Fclock
DCYI
t
IT
Input Clock frequency DM2509
Input Clock frequency DM2509-166
Input clock duty cycle
Input Clock Transition Time
Stabilization Time
Parameter
Min.
25
25
40
Max.
125
166
60
4.5
1
Units
MHz
%
ns
ms
D M E L
3
DM2509
Preliminary
AC Electrical Characteristics
Symbol
t
PE
t
JC
t
SK
t
D
t
r
t
f
(Over the Operating Range: 0°C
≤
T
A
≤
+70°C, V
CC
= 3.3V± 10%
)
Parameter
Phase Error
Jitter, cycle-to-
cycle
Skew, Output-to-
Output
Duty cycle
From (Input)
CLKIN
↑
at 66 MHz to 100MHz
Any Output or FBOUT to CLK
in, at 100MHz and 66MHz
Any Y or FBOUT with equal
loads
F (CLKIN > 80 MHz)
F(CLKIN
≤
80MHz)
To (Output)
FBIN
↑
Output or FBOUT
to CLK n+1
Min
-350
-100
-100
Typ
Max
350
100
Units
ps
100
58
55
1.0
1.1
ns
%
Any Y or FBOUT
43
45
Output Rise Time
Output Fall Time
0.4V to 2.0V, 30pF load
2.0V to 0.4V, 30pF load
Note: Parameters are guaranteed by characterization
D M E L
4
DM2509
Package Drawing
Preliminary
Package
A24
N
28 Lead
e
0.65
E1
4.4
D
7.8
E
6.4
A
1.20mm (MAX)
A2
0.90
Note: All dimensions in millimeters (mm)
Ordering Information
Part Number
DM2509A
DM2509A-166
DM2509K
DM2509K-166
Package
24-pin TSSOP
24-pin TSSOP
24-pin TVSOP
24-pin TVSOP
Speed Grade
25MHz - 125MHz
25MHz - 166MHz
25MHz - 125MHz
25MHz - 166MHz
D M E L
5
京公网安备 11010802033920号
EEWORLD
