WS512K32V-XXX
HI-RELIABILITY PRODUCT
512Kx32 SRAM 3.3V MODULE
FEATURES
s
Access Times of 70, 85, 100, 120ns
s
Packaging
• 66-pin, PGA Type, 1.185 inch square, Hermetic
Ceramic HIP (Package 401)
ADVANCED*
s
Low Voltage
• 3.3V
±10%
Power Supply
s
Low Power CMOS
s
Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
s
Weight
WS512K32V-XG2TX - 8 grams typical
WS512K32V-XHX - 13 grams typical
* This data sheet describes a product that may or may not be under development
and is subject to change or cancellation without notice.
• 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880 inch) square
4.57mm (0.180 inch) high (Package 509). Designed to fit
JEDEC 68 lead 0.990" CQFJ footprint.
s
Organized as 512Kx32, User Configurable as 1024Kx16 or
2Mx8
s
Commercial, Industrial and Military Temperature Ranges
s
TTL Compatible Inputs and Outputs
FIG. 1
1
I/O
8
I/O
9
I/O
10
A
13
A
14
A
15
A
16
A
17
I/O
0
I/O
1
I/O
2
11
PIN CONFIGURATION FOR WS512K32V-XHX
TOP VIEW
12
WE
2
CS
2
GND
I/O
11
A
10
A
11
A
12
V
CC
CS
1
NC
I/O
3
22
33
23
I/O
15
I/O
14
I/O
13
I/O
12
OE
A
18
WE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
6
A
7
NC
A
8
A
9
I/O
16
I/O
17
I/O
18
44
34
V
CC
CS
4
WE
4
I/O
27
A
3
A
4
A
5
WE
3
CS
3
GND
I/O
19
55
45
I/O
31
I/O
30
I/O
29
I/O
28
A
0
A
1
A
2
I/O
23
I/O
22
I/O
21
I/O
20
8
8
8
8
PIN DESCRIPTION
56
I/O
0
-
31
A
0-18
WE
1-4
CS
1-4
OE
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
BLOCK DIAGRAM
W E
1
CS
1
OE
A
0
-
18
512K x 8
512K x 8
W E
2
CS
2
W E
3
CS
3
W E
4
CS
4
512K x 8
512K x 8
66
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
February 2000 Rev. 2
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WS512K32V-XXX
FIG. 2
PIN CONFIGURATION FOR WS512K32V-XG2TX
TOP VIEW
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
3
GND
CS
4
WE
1
A
6
A
7
A
8
A
9
A
10
V
CC
PIN DESCRIPTION
I/O
0
-
31
A
0-18
WE
1-4
CS
1-4
OE
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
V
CC
A
11
A
12
A
13
A
14
A
15
A
16
CS
1
OE
CS
2
A
17
WE
2
WE
3
WE
4
A
18
NC
NC
OE
A
0
-
18
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
0.940"
The WEDC 68 lead G2T CQFP
fills the same fit and function as
the JEDEC 68 lead CQFJ or 68
PLCC. But the G2T has the TCE
and lead inspection advantage of
the CQFP form.
BLOCK DIAGRAM
W E
1
CS
1
W E
2
CS
2
W E
3
CS
3
W E
4
CS
4
512K x 8
512K x 8
512K x 8
512K x 8
8
8
8
8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
2
WS512K32V-XXX
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
Symbol
T
A
T
STG
V
G
T
J
V
CC
-0.5
Min
-55
-65
-0.5
Max
+125
+150
Vcc+0.5
150
4.0
Unit
°C
°C
V
°C
V
Parameter
OE Capacitance
WE Capacitance
HIP (PGA)
CQFP G2T
CS Capacitance
Data I/O Capacitance
Address Input Capacitance
V
V
V
°C
CS
H
L
L
L
OE
X
L
H
X
WE
X
H
H
L
TRUTH TABLE
Mode
Standby
Read
Out Disable
Write
Data I/O
High Z
Data Out
High Z
Data In
Power
Standby
Active
Active
Active
CAPACITANCE
(T
A
= +25°C)
Symbol
C
OE
C
WE
Conditions
V
IN
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
20
15
C
CS
C
I/O
C
AD
V
IN
= 0 V, f = 1.0 MHz
V
I/O
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
20
20
50
pF
pF
pF
Max
50
Unit
pF
pF
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp (Mil)
Symbol
V
CC
V
IH
V
IL
T
A
Min
3.0
2.2
-0.5
-55
Max
3.6
V
CC
+ 0.3
+0.8
+125
Unit
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
(V
CC
= 3.3V, V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current x 32 Mode
Standby Current
Output Low Voltage
Output High Voltage
Symbol
I
LI
I
LO
I
CC x 32
I
SB
V
OL
V
OH
Conditions
Min
V
CC
= 3.6, V
IN
= GND to V
CC
CS = V
IH
, OE = V
IH
, V
OUT
= GND to V
CC
CS = V
IL
, OE = V
IH
, f = 5MHz, Vcc = 3.6
CS = V
IH
, OE = V
IH
, f = 5MHz, Vcc = 3.6
I
OL
= 2.1mA, V
CC
= 3.0
I
OH
= -1.0mA, V
CC
= 3.0
2.4
Max
10
10
100
2.0
0.4
Units
µA
µA
mA
mA
V
V
NOTE: DC test conditions: V
IH
= V
CC
-0.3V, V
IL
= 0.3V
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WS512K32V-XXX
AC CHARACTERISTICS
(V
CC
= 3.3V, V
SS
=0V, T
A
= -55°C to +125°C)
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
t
RC
t
AA
t
OH
t
ACS
t
OE
t
CLZ
1
Symbol
Min
70
-70
Max
Min
85
70
5
70
35
10
5
25
25
10
5
5
-85
Max
Min
100
85
5
85
40
10
5
25
25
-100
Max
Min
120
100
5
100
50
10
5
35
35
-120
Max
Units
ns
120
ns
ns
120
60
ns
ns
ns
ns
35
35
ns
ns
t
OLZ
1
t
CHZ
1
t
OHZ
1
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS
(V
CC
= 3.3V, V
SS
=0V, T
A
= -55°C to +125°C)
Parameter
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold from Write Time
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW
1
t
WHZ
t
DH
1
Symbol
Min
70
60
60
30
50
0
5
5
-70
Max
Min
85
75
75
30
50
0
5
5
25
0
0
-85
Max
Min
100
80
80
40
60
0
5
5
25
0
-100
Max
Min
120
100
100
40
60
0
5
5
35
0
-120
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
35
ns
ns
1. This parameter is guaranteed by design but not tested.
FIG. 3
AC TEST CIRCUIT
Current Source
I
OL
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
D.U.T.
V
Z
Typ
V
IL
= 0, V
IH
= 2.5
5
1.5
1.5
Unit
V
ns
V
V
≈
1.5V
Output Timing Reference Level
C
eff
= 50 pf
(Bipolar Supply)
I
OH
Current Source
NOTES:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z
0
= 75
Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
4
WS512K32V-XXX
FIG. 4
TIMING WAVEFORM - READ CYCLE
ADDRESS
t
RC
t
AA
CS
t
RC
ADDRESS
t
ACS
t
CLZ
OE
t
CHZ
t
AA
t
OH
DATA I/O
PREVIOUS DATA VALID
DATA VALID
t
OE
t
OLZ
DATA I/O
HIGH IMPEDANCE
t
OHZ
DATA VALID
READ CYCLE 1 (CS = OE = V
IL
, WE = V
IH
)
READ CYCLE 2 (WE = V
IH
)
FIG. 5
WRITE CYCLE - WE CONTROLLED
t
WC
ADDRESS
t
AW
t
CW
CS
t
AH
t
AS
WE
t
WP
t
OW
t
WHZ
t
DW
t
DH
DATA I/O
DATA VALID
WRITE CYCLE 1, WE CONTROLLED
FIG. 6
WRITE CYCLE - CS CONTROLLED
t
WC
ADDRESS
WS32K32-XHX
t
CW
t
AH
t
AS
CS
t
AW
t
WP
WE
t
DW
DATA I/O
DATA VALID
t
DH
WRITE CYCLE 2, CS CONTROLLED
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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