Philips Semiconductors
Product specification
Image reject 1800 MHz transceiver
for DECT applications
FEATURES
•
Receiver with:
– low noise amplifier
– dual quadrature mixers for image rejection
(lower sideband)
– I and Q combining networks at a fixed IF
•
Both high-frequency and low-frequency VCOs including
buffers with good isolation for low pulling
•
Transmitter with:
– dual quadrature mixers for image rejection
(lower sideband)
– amplitude ramping circuit
– amplifier with high output power.
APPLICATIONS
•
1800 MHz transceiver for DECT hand-portable
equipment
•
TDMA systems.
GENERAL DESCRIPTION
The UAA2067G is a low-power transceiver intended for
use in portable and base station transceivers complying
with the DECT system. The IC performs in accordance
with specifications in the
−30
to +85°C temperature range.
The UAA2067G contains a front-end receiver for the
1800 to 1900 MHz frequency range, a high-frequency
VCO for the 1650 to 1850 MHz range, a low-frequency
VCO for the 100 to 140 MHz frequency range and a
transmitter with a high-output power amplifier driver stage
for the 1800 to 1900 MHz frequency range. Designed in
an advanced BiCMOS process, it combines high
performance with low-power consumption and a high
degree of integration, thus reducing external component
costs and total radio size.
Its first advantage is to provide typically 34 dB of image
rejection in the receiver path. Thus, the image filter
between the LNA and the mixer is redundant and
consequently can be removed. The receive section
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
UAA2067G
LQFP32
DESCRIPTION
UAA2067G
consists of a low-noise amplifier that drives a quadrature
mixer pair. Image rejection is achieved by this RF mixer
pair and the two phase shifters in the I and Q channels that
phase shift the IF by 45° and 135° respectively. The two
phase shifted IFs are recombined and buffered to furnish
the IF output signal.
Signals presented at the RF input at LO
−
IF frequency are
rejected through this signal processing while signals at
LO + IF frequency can form the IF signal.
Its second advantage is to provide a good buffered
high-frequency VCO signal to the RX and TX mixers and
to the synthesizer-prescaler. Switching the receive or
transmit section
on
gives a very small change in VCO
frequency.
Its third advantage is to provide a good buffered
low-frequency VCO signal to the TX mixers, to the
synthesizer-prescaler and the second down conversion
mixer in a double conversion receiver. Switching the
transmit section
on
gives a very small change in
VCO frequency.
The frequency of each VCO is determined by a resonator
network that is external to the IC. Each VCO has a
regulated power supply voltage that has been designed
specifically for minimizing a change in frequency due to
changes in the power supply voltage, which may be
caused for instance by switching
on
the power amplifier.
Its fourth advantage is to provide typically 33 dBc of image
rejection in the single-sideband up-conversion mixer. Thus
the image filter between the power amplifier and the
antenna is redundant and may consequently be removed.
Image rejection is achieved in the internal architecture by
two RF mixers in quadrature and two phase shifters in the
low-frequency VCO signal that shifts the phase to
0° and 90°. The output signals of the mixers are summed
to form the single-upper-sideband output signal.
The output stage is a high-level output buffer with an
output power of approximately 4 dBm. The output level is
sufficient to drive a three-stage bipolar preamplifier
for DECT.
VERSION
SOT401-1
plastic low profile quad flat package; 32 leads; body 5
×
5
×
1.4 mm
1996 Oct 22
2
Philips Semiconductors
Product specification
Image reject 1800 MHz transceiver
for DECT applications
PINNING
SYMBOL
PDIFLO
IFLOREG
GND1
IFLOO
V
CC(IFLO)
IFLORES
GND2
ICEN
PDTX
TXRAMP
V
CC(TX)
TXB
TXA
GND3
PDRFLO
V
CC(RFLOO)
RFLOO
V
CC1(RFLO)
GND4
RFLOA
RFLOB
GND5
V
CC2(RFLO)
RFLOREG
IFO
IFDEC
V
CC(MIX)
RXA
RXB
GND6
PDRX
GND7
Notes
1. Pins 3 and 7 are internally short-circuited.
2. Pins 11 and 27 should be at the same DC voltage.
3. Pins 18 and 23 are internally short-circuited.
4. Pins 19 and 22 are internally short-circuited.
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
power-down for IFLO
regulator decoupling for IFLO
ground for IFLO; note 1
IFLO output
supply voltage for IFLO
IFLO resonator
ground for IFLO resonator; note 1
IC enable
power-down for transmitter
power ramping transmitter
supply voltage for transmitter output stage; note 2
transmitter RF output B
transmitter RF output A
ground for transmitter output stage
power-down for RFLO
supply voltage for RFLO output
RFLO output
supply voltage for RFLO oscillator; note 3
ground for RFLO oscillator; note 4
RFLO resonator
RFLO resonator
ground for RFLO oscillator; note 4
supply voltage for RFLO oscillator; note 3
regulator decoupling for RFLO
receiver IF output
IF decoupling
supply voltage for receive and transmit mixers; note 2
receiver RF input A
receiver RF input B
ground for receive and transmit mixers
power-down for receiver
die-pad ground
DESCRIPTION
UAA2067G
1996 Oct 22
5
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