AT29C256 datasheet, PDF - EEWORLD Datasheet

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AT29C256: Description32K X 8 FLASH 5V PROM, 90 ns, PQCC32; Categorystorage; File Size321KB，17 Pages; ManufacturerAtmel (Microchip)

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AT29C256 Overview

32K X 8 FLASH 5V PROM, 90 ns, PQCC32

AT29C256 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	32
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	5.5 V
Minimum supply/operating voltage	4.5 V
Rated supply voltage	5 V
maximum access time	90 ns
Processing package description	Plastic, MS-016AE, LCC-32
state	DISCONTINUED
Craftsmanship	CMOS
packaging shape	Rectangle
Package Size	ChipCARRIER
surface mount	Yes
Terminal form	J BEND
Terminal spacing	1.27 mm
terminal coating	tin lead
Terminal location	Four
Packaging Materials	Plastic/Epoxy
Temperature level	INDUSTRIAL
memory width	8
organize	32K × 8
storage density	262144 deg
operating mode	ASYNCHRONOUS
Number of digits	32768 words
Number of digits	32K
Memory IC type	FLASH 5V programmable read-only memory
serial parallel	parallel
Maximum TWC of write cycle	10 ms

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Features

•

Fast Read Access Time – 70 ns

•

5-volt Only Reprogramming

•

Page Program Operation

•

– Single Cycle Reprogram (Erase and Program)

– Internal Address and Data Latches for 64 Bytes

Internal Program Control and Timer

Hardware and Software Data Protection

Fast Program Cycle Times

– Page (64 Byte) Program Time – 10 ms

– Chip Erase Time – 10 ms

DATA Polling for End of Program Detection

Low-power Dissipation

– 50 mA Active Current

– 300 µA CMOS Standby Current

Typical Endurance > 10,000 Cycles

Single 5V

10% Supply

CMOS and TTL Compatible Inputs and Outputs

Commercial and Industrial Temperature Ranges

256K (32K x 8)

5-volt Only

Flash Memory

AT29C256

Description

The AT29C256 is a five-volt-only in-system Flash programmable and erasable read

only memory (PEROM). Its 256K of memory is organized as 32,768 words by 8 bits.

Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers

access times to 70 ns with power dissipation of just 275 mW. When the device is

deselected, the CMOS standby current is less than 300 µA. The device endurance is

such that any sector can typically be written to in excess of 10,000 times.

Pin Configurations

Pin Name

A0 - A14

I/O0 - I/O7

Function

Addresses

Chip Enable

Output Enable

Write Enable

Data Inputs/Outputs

No Connect

Don’t Connect

A11

A13

A14

VCC

A12

TSOP Top View

Type 1

A10

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

PLCC and LCC Top View

A12

VCC

A14

A13

Note:

PLCC package pins 1 and 17 are

DON’T CONNECT.

I/O1

I/O2

GND

I/O3

I/O4

I/O5

I/O0

A11

A10

I/O7

I/O6

Rev. 0046P–FLASH–10/04

AT29C256

PROGRAM:

The device is reprogrammed on a page basis. If a byte of data within a

page is to be changed, data for the entire page must be loaded into the device. Any byte

that is not loaded during the programming of its page will be indeterminate. Once the

bytes of a page are loaded into the device, they are simultaneously programmed during

the internal programming period. After the first data byte has been loaded into the

device, successive bytes are entered in the same manner. Each new byte to be pro-

grammed must have its high-to-low transition on WE (or CE) within 150 µs of the low-to-

high transition of WE (or CE) of the preceding byte. If a high-to-low transition is not

detected within 150 µs of the last low-to-high transition, the load period will end and the

internal programming period will start. A6 to A14 specify the page address. The page

address must be valid during each high-to-low transition of WE (or CE). A0 to A5 specify

the byte address within the page. The bytes may be loaded in any order; sequential

loading is not required. Once a programming operation has been initiated, and for the

duration of t

, a read operation will effectively be a polling operation.

SOFTWARE DATA PROTECTION:

A software controlled data protection feature is

available on the AT29C256. Once the software protection is enabled a software algo-

rithm must be issued to the device before a program may be performed. The software

protection feature may be enabled or disabled by the user; when shipped from Atmel,

the software data protection feature is disabled. To enable the software data protection,

a series of three program commands to specific addresses with specific data must be

performed. After the software data protection is enabled the same three program com-

mands must begin each program cycle in order for the programs to occur. All software

program commands must obey the page program timing specifications. Once set, the

software data protection feature remains active unless its disable command is issued.

Power transitions will not reset the software data protection feature, however the soft-

ware feature will guard against inadvertent program cycles during power transitions.

Once set, software data protection will remain active unless the disable command

sequence is issued.

After setting SDP, any attempt to write to the device without the three-byte command

sequence will start the internal write timers. No data will be written to the device; how-

ever, for the duration of t

, a read operation will effectively be a polling operation.

After the software data protection’s three-byte command code is given, a byte load is

performed by applying a low pulse on the WE or CE input with CE or WE low (respec-

tively) and OE high. The address is latched on the falling edge of CE or WE, whichever

occurs last. The data is latched by the first rising edge of CE or WE. The 64 bytes of

data must be loaded into each sector by the same procedure as outlined in the program

section under device operation.

HARDWARE DATA PROTECTION:

Hardware features protect against inadvertent

programs to the AT29C256 in the following ways: (a) V

sense – if V

is below 3.8V

(typical), the program function is inhibited; (b) V

power on delay – once V

has

reached the V

sense level, the device will automatically time out 5 ms (typical) before

programming; (c) Program inhibit – holding any one of OE low, CE high or WE high

inhibits program cycles; and (d) Noise filter – pulses of less than 15 ns (typical) on the

WE or CE inputs will not initiate a program cycle.

0046P–FLASH–10/04

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