AT48801
Features
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Compatible with MCS-51
™
Products
8K bytes of On-Board Program Memory
Fully Static Operation: 0 Hz to 16 MHz
256 x 8 Bit Internal RAM
32 Programmable I/O Lines
Three 16 Bit Timer/Counters
Eight Interrupt Sources
Programmable Serial Channel
Low Power Idle and Power Down Modes
Description
The AT48801 is a low-power, high-performance CMOS 8 bit microcomputer with 8K
bytes on-board program memory. The device is compatible with the industry standard
80C51 and 80C52 instruction set and pinout. The Atmel AT48801 is a powerful micro-
computer which provides a highly flexible and cost effective solution to spread-spec-
trum applications.
The AT48801 provides the following standard features: 8K bytes of program memory,
256-bytes of RAM, 32 I/O lines, three 16 bit timer/counters, a six-vector two-level
interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In
addition, the AT48801 is designed with static logic for operation down to zero fre-
quency and supports two software selectable power saving modes. The Idle Mode
stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt sys-
tem to continue functioning. The Power Down Mode saves the RAM contents but
freezes the oscillator, disabling all other chip functions until the next hardware reset.
8 Bit
Spread-
Spectrum
Microcontroller
Preliminary
Pin Configuration
PQFP
0629A
1-1
Block Diagram
1-2
AT48801
AT48801
Pin Description
V
CC
Supply voltage.
GND
Ground.
Port 0
Port 0 is an 8 bit open drain bidirectional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high-im-
pedance inputs.
Port 0 can also be configured to be the multiplexed low-or-
der address/data bus during accesses to external pro-
gram and data memory. In this mode, P0 has internal pul-
lups.
Port 1
Port 1 is an 8 bit bidirectional I/O port with internal pullups.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (I
IL
) because of the internal pullups.
In addition, P1.0 and P1.1 can be configured to be the
timer/counter 2 external count input (P1.0/T2) and the
timer/counter 2 trigger input (P1.1/T2EX), respectively, as
shown in the following table.
Port Pin
P1.0
P1.1
Port 2
Port 2 is an 8 bit bidirectional I/O port with internal pullups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source
current (I
IL
) because of the internal pullups.
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16 bit addresses (MOVX
@ DPTR). In this application, Port 2 uses strong internal
pullups when emitting 1s. During accesses to external
data memory that use 8 bit addresses (MOVX @ RI), Port
2 emits the contents of the P2 Special Function Register.
Port 3
Port 3 is an 8 bit bidirectional I/O port with internal pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins, they are pulled high by
Alternate Functions
T2 (external count input to
Timer/Counter 2), clock-out
T2EX (Timer/Counter 2 capture/reload
trigger and direction control)
RST
Reset input. A high on this pin for two machine cycles
while the oscillator is running resets the device.
ALE
Address Latch Enable is an output pulse for latching the
low byte of the address during accesses to external mem-
ory.
In normal operation, ALE is emitted at a constant rate of
1/6 the oscillator frequency and may be used for external
timing or clocking purposes. Note, however, that one ALE
pulse is skipped during each access to external data
memory.
If desired, ALE operation can be disabled by setting bit 0
of SFR location 8EH. With the bit set, ALE is active only
during a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no ef-
fect if the microcrontroller is in external execution mode.
PSEN
Program Store Enable is the read strobe to external pro-
gram memory.
When the AT48801 is executing code from external pro-
gram memory, PSEN is activated twice each machine cy-
cle, except that two PSEN activations are skipped during
each access to external data memory.
EA
External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external pro-
gram memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be
internally latched on reset.
EA should be strapped to V
CC
for internal program execu-
tions.
(continued)
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Functions
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (timer 0 external input)
T1 (timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (I
IL
) because of the pullups.
Port 3 also serves the functions of various special features
of the AT89C51, as shown in the following table.
1-3
Pin Description
(Continued)
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Note that not all of the addresses are occupied, and unoc-
cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indetermi-
nate effect.
User software should not write 1s to these unlisted loca-
tions, since they may be used in future products to invoke
new features. In that case, the reset or inactive values of
the new bits will always be 0.
Timer 2 Registers
Control and status bits are contained
in registers T2CON (shown in Table 2) and T2MOD
(shown in Table 4) for Timer 2. The register pair
Special Function Registers
A map of the on-chip memory area called the Special
Function Register (SFR) space is shown in Table 1.
(continued)
Table 1.
AT48801 SFR Map and Reset Values
0F8H
0F0H
0E8H
0E0H
0D8H
0D0H
0C8H
0C0H
0B8H
0B0H
0A8H
0A0H
98H
90H
88H
80H
IP
XX000000
P3
11111111
IE
0X000000
P2
11111111
SCON
00000000
P1
11111111
TCON
00000000
P0
11111111
TMOD
00000000
SP
00000111
TL0
00000000
DPL
00000000
TL1
00000000
DPH
00000000
TH0
00000000
TH1
00000000
PCON
0XXX0000
SBUF
XXXXXXXX
PSW
00000000
T2CON
00000000
T2MOD
XXXXXX00
RCAP2L
00000000
RCAP2H
00000000
TL2
00000000
TH2
00000000
ACC
00000000
B
00000000
0FFH
0F7H
0EFH
0E7H
0DFH
0D7H
0CFH
0C7H
0BFH
0B7H
0AFH
0A7H
9FH
97H
8FH
87H
1-4
AT48801
AT48801
Table 2.
T2CON—Timer/Counter 2 Control Register
T2CON Address = 0C8H
Bit Addressable
TF2
Bit
Symbol
TF2
EXF2
7
EXF2
6
Function
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be
set when either RCLK = 1 or TCLK = 1.
Timer 2 external flag set when either a capture or reload is caused by a negative transition on
T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector
to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an
interrupt in up/down counter mode (DCEN = 1).
Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its
receive clock in serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the
receive clock.
Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its
transmit clock in serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for
the transmit clock.
Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative
transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer
2 to ignore events at T2EX.
Start/Stop control for Timer 2. TR2 = 1 starts the timer.
Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event
counter (falling edge triggered).
Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if
EXEN2 = 1. CP/RL2 = 0 causes automatic reloads to occur when Timer 2 overflows or negative
transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored
and the timer is forced to auto-reload on Timer 2 overflow.
When an instruction accesses an internal location above
address 7FH, the address mode used in the instruction
specifies whether the CPU accesses the upper 128-bytes
of RAM or the SFR space. Instructions that use direct ad-
dressing access SFR space.
For example, the following direct addressing instruction
accesses the SFR at location 0A0H (which is P2).
MOV 0A0H, #data
Instructions that use indirect addressing access the upper
128-bytes of RAM. For example, the following indirect ad-
dressing instruction, where R0 contains 0A0H, accesses
the data byte at address 0A0H, rather than P2 (whose ad-
dress is 0A0H).
(continued)
RCLK
5
TCLK
4
EXEN2
3
TR2
2
C/T2
1
CP/RL2
0
Reset Value = 0000 0000B
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Special Function Registers
(Continued)
(RCAP2H, RCAP2L) are the Capture/Reload registers for
Timer 2 in 16 bit capture mode or 16 bit auto-reload mode.
Interrupt Registers
The individual interrupt enable bits
are in the IE register. Two priorities can be set for each of
the six interrupt sources in the IP register.
Data Memory
The AT48801 implements 256-bytes of on-chip RAM. The
upper 128-bytes occupy a parallel address space to the
Special Function Registers. That means the upper 128-
bytes have the same addresses as the SFR space but are
physically separate from SFR space.
1-5
DSP and ARM Processors
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