Features
•
•
•
•
•
•
•
•
•
•
•
Single Supply for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV)
Fast Read Access Time - 120 ns
Internal Program Control and Timer
16K bytes Boot Block With Lockout
Fast Erase Cycle Time - 10 seconds
Byte-By-Byte Programming - 30
µs/Byte
Typical
Hardware Data Protection
DATA Polling For End Of Program Detection
Low Power Dissipation
- 25 mA Active Current
- 50
µA
CMOS Standby Current
Typical 10,000 Write Cycles
Small Packaging
- 8 x 14 mm CBGA
Description
The AT49BV/LV080 are 3-volt-only in-system Flash Memory devices. Their 8 mega-
bits of memory are organized as 1,024,576 words by 8 bits. Manufactured with At-
mel’s advanced nonvolatile CMOS technology, the devices offer access times to 120
ns with power dissipation of just 90 mW over the commercial temperature range.
When the device is deselected, the CMOS standby current is less than 50
µA.
The device contains a user-enabled "boot block" protection feature. Two versions of
the feature are available: the AT49BV/LV080 locates the boot block at lowest order
addresses ("bottom boot"); the AT49BVLV080T locates it at highest order addresses
("top boot").
(continued)
8-Megabit
(1M x 8)
Single 2.7-volt
Battery-Voltage
™
Flash Memory
AT49BV080
AT49BV080T
AT49LV080
AT49LV080T
Pin Configurations
Pin Name
A0 - A19
CE
OE
WE
RESET
RDY/BUSY
I/O0 - I/O7
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
Ready/Busy Output
Data Inputs/Outputs
TSOP Top View
Type 1
CBGA Top View
1
2
3
4
5
6
7
NC
RESET
A11
A10
A9
A8
A7
A6
A5
A4
NC
NC
A3
A2
A1
A0
I/O0
I/O1
I/O2
I/O3
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SOIC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VCC
CE
A12
A13
A14
A15
A16
A17
A18
A19
NC
NC
NC
NC
WE
OE
RDY/BUSY
I/O7
I/O6
I/O5
I/O4
VCC
A
A5
B
A4
C
A6
D
A3 I/O1 NC VCC I/O4 I/O7 NC
E
A2
F
A1 I/O0 I/O2 GND I/O5 RY/BY WE
A0 I/O3 GND I/O6 OE NC
A9 RST CE A14 A16 A19
A7 A10 VCC A13 NC A18
A8 A11 NC A12 A15 A17
0812A–8/97
Description
(Continued)
To allow for simple in-system reprogrammability, the
AT49BV/LV080 does not require high input voltages for
programming. 3-volt-only commands determine the read
and programming operation of the device. Reading data
out of the device is similar to reading from an EPROM.
Reprogramming the AT49BV/LV080 is performed by eras-
ing the entire 8 megabits of memory and then program-
ming on a byte-by-byte basis. The typical byte program-
ming time is a fast 30
µs.
The end of a program cycle can
be optionally detected by the DATA polling feature. Once
the end of a byte program cycle has been detected, a new
access for a read or program can begin. The typical num-
ber of program and erase cycles is in excess of 10,000
cycles.
The optional 16K bytes boot block section includes a re-
programming write lock out feature to provide data integ-
rity. The boot sector is designed to contain user secure
code, and when the feature is enabled, the boot sector is
permanently protected from being reprogrammed.
Block Diagram
V
CC
GND
OE
WE
CE
AT49BV/LV080
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
OE, CE, AND WE
LOGIC
DATA LATCH
INPUT/OUTPUT
BUFFERS
Y-GATING
FFFFFH
X DECODER
MAIN MEMORY
(1008K BYTES)
03FFFH
OPTIONAL BOOT
BLOCK (16K BYTES)
00000H
AT49BV/LV080T
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
DATA LATCH
INPUT/OUTPUT
BUFFERS
Y-GATING
FFFFFH
OPTIONAL BOOT
BLOCK (16K BYTES)
FC000H
MAIN MEMORY
(1008K BYTES)
00000H
Y DECODER
ADDRESS
INPUTS
Device Operation
READ:
The AT49BV/LV080 is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-
line control gives designers flexibility in preventing bus
contention.
ERASURE:
Before a byte can be reprogrammed, the
1024K bytes memory array (or 1008K bytes if the boot
block featured is used) must be erased. The erased state
of the memory bits is a logical “1”. The entire device can
be erased at one time by using a 6-byte software code.
The software chip erase code consists of 6-byte load com-
mands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is t
EC
. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
BYTE PROGRAMMING:
Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the in-
ternal device command register and is a 4 bus cycle op-
eration (please refer to the Command Definitions table).
The device will automatically generate the required inter-
nal program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified t
BP
cy-
cle time. The DATA polling feature may also be used to
indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT:
The de-
vice has one designated block that has a programming
lockout feature. This feature prevents programming of
data in the designated block once the feature has been
enabled. The size of the block is 16K bytes. This block,
referred to as the boot block, can contain secure code that
is used to bring up the system. Enabling the lockout fea-
ture will allow the boot code to stay in the device while data
in the rest of the device is updated. This feature does not
have to be activated; the boot block’s usage as a write
protected region is optional to the user. The address
range of the AT49BV/LV080 boot block is 00000H to
03FFFH while the address range of the AT49BV/LV080T
boot block is FC000H to FFFFFH.
To activate the lockout feature, a series of six program
commands to specific addresses with specific data must
2
AT49BV/LV080
AT49BV/LV080
Device Operation
(Continued)
be performed. Please refer to the Command Definitions
table.
BOOT BLOCK LOCKOUT DETECTION:
A software
method is available to determine if programming of the
boot block section is locked out. When the device is in the
software product identification mode (see Software Prod-
uct Identification Entry and Exit sections) a read from ad-
dress location 00002H will show if programming the boot
block is locked out. If the data on I/O0 is low, the boot
block can be programmed; if the data on I/O0 is high, the
program lockout feature has been activated and the block
cannot be programmed. The software product identifica-
tion exit code should be used to return to standard opera-
tion.
BOOT BLOCK PROGRAMMING LOCKOUT OVER-
RIDE:
The user can override the boot block programming
lockout by taking the RESET pin to 12 + 0.5 volts. By doing
this, protected boot block data can be altered through a
chip erase, or byte programming. When the RESET pin is
brought back to TTL levels the boot block programming
lockout feature is again active.
PRODUCT IDENTIFICATION:
The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING:
The AT49BV/LV080 features DATA
polling to indicate the end of a program cycle. During a
program cycle an attempted read of the last byte loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. DATA
polling may begin at any time during the program cycle.
TOGGLE BIT:
I n a d d i t i o n t o DATA po ll in g, t he
AT49BV/LV080 provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from
the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
RDY/BUSY:
An open drain READY/BUSY output pin pro-
vides another method of detecting the end of a program or
erase operation. RDY/BUSY is actively pulled low during
the internal program and erase cycles and is released at
the completion of the cycle. The open drain connection al-
lows for OR - tying of several devices to the same
RDY/BUSY line.
RESET:
A RESET input pin is provided to ease some
system applications. When RESET is at a logic high level,
the device is in its standard operating mode. A low level on
the RESET input halts the present device operation and
puts the outputs of the device in a high impedance state.
If the RESET pin makes a high to low transition during a
program or erase operation, the operation may not be suc-
cessfully completed, and the operation will have to be re-
peated after a high level is applied to the RESET pin.
When a high level is reasserted on the RESET pin, the
device returns to the read or standby mode, depending
upon the state of the control inputs. By applying a 12V +
0.5V input signal to the RESET pin the boot block array
can be reprogrammed even if the boot block lockout fea-
ture has been enabled (see Boot Block Programming
Lockout Override section).
HARDWARE DATA PROTECTION:
Hardware features
protect against inadvertent programs to the
AT49BV/LV080 in the following ways: (a) V
CC
sense: if
V
CC
is below 1.8V (typical), the program function is inhib-
ited. (b) Program inhibit: holding any one of OE low, CE
high or WE high inhibits program cycles. (c) Noise filter:
pulses of less than 15 ns (typical) on the WE or CE inputs
will not initiate a program cycle.
3
Command Definition (in Hex)
Command
Bus
Sequence
Cycles
Read
Chip Erase
Byte
Program
Boot Block
(1)
Lockout
Product ID
Entry
Product ID
(2)
Exit
Product ID
(2)
Exit
1
6
4
6
3
3
1
1st Bus
Cycle
Addr
Addr
5555
5555
5555
5555
5555
XXXX
Data
D
OUT
AA
AA
AA
AA
AA
F0
2nd Bus
Cycle
Addr
2AAA
2AAA
2AAA
2AAA
2AAA
Data
55
55
55
55
55
3rd Bus
Cycle
Addr
5555
5555
5555
5555
5555
Data
80
A0
80
90
F0
4th Bus
Cycle
Addr
5555
Addr
5555
Data
AA
D
IN
AA
5th Bus
Cycle
Addr
2AAA
Data
55
6th Bus
Cycle
Addr
5555
Data
10
2AAA
55
5555
40
Notes: 1. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49BV/LV080 and FC000H to FFFFFH for the
AT49BV/LV080T.
2. Either one of the Product ID Exit commands can be used.
Absolute Maximum Ratings*
Temperature Under Bias................. -55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
CC
+ 0.6V
Voltage on OE
with Respect to Ground ................... -0.6V to +13.5V
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
4
AT49BV/LV080
AT49BV/LV080
DC and AC Operating Range
AT49BV/LV080-12
Operating
Temperature (Case)
V
CC
Power Supply
Com.
Ind.
0°C - 70°C
-40°C - 85°C
2.7V - 3.6V / 3.0V - 3.6V
AT49BV/LV080-15
0°C - 70°C
-40°C - 85°C
2.7V - 3.6V / 3.0V - 3.6V
AT49BV/LV080-20
0°C - 70°C
-40°C - 85°C
2.7V - 3.6V / 3.0V - 3.6V
Operating Modes
Mode
Read
Program
(2)
Standby/Write
Inhibit
Program Inhibit
Program Inhibit
Output Disable
RESET
Product
Identification
Hardware
Software
(5)
Notes: 1. X can be V
IL
or V
IH
.
2. Refer to AC Programming Waveforms.
3. V
H
= 12.0V
±
0.5V.
CE
V
IL
V
IL
V
IH
X
X
X
X
OE
V
IL
V
IH
X
(1)
X
V
IL
V
IH
X
WE
V
IH
V
IL
X
V
IH
X
X
X
RESET
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IL
Ai
Ai
Ai
X
I/O
D
OUT
D
IN
High Z
RDY/BUSY
V
OH
V
OL
V
OH
V
OH
V
OH
High Z
X
V
OH
High Z
V
IL
V
IL
V
IH
V
IH
A1 - A19 = V
IL
, A9 = V
H
,
(3)
A0 = V
IL
A1 - A19 = V
IL
, A9 = V
H
,
(3)
A0 = V
IH
A0 = V
IL
, A1 - A19 = V
IL
A0 = V
IH
, A1 - A19 = V
IL
Manufacturer Code
(4)
Device Code
(4)
Manufacturer Code
(4)
Device Code
(4)
4. Manufacturer Code: 1FH,
Device Code: 23H (AT49BV/LV080), 27H (AT49BV/LV080T)
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
I
LI
I
LO
I
SB1
I
SB2
I
CC (1)
V
IL
V
IH
V
OL
V
OH
Parameter
Input Load Current
Output Leakage Current
V
CC
Standby Current CMOS
V
CC
Standby Current TTL
V
CC
Active Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I
OL
= 1.6 mA, V
CC
= 3.0V
I
OH
= -100
µA,
V
CC
= 3.0V
2.4
2.0
0.45
Condition
V
IN
= 0V to V
CC
V
I/O
= 0V to V
CC
CE = V
CC
- 0.3V to V
CC
CE = 2.0V to V
CC
f = 5 MHz; I
OUT
= 0 mA, V
CC
= 3.6V
Min
Max
1
1
50
1
25
0.6
Units
µA
µA
µA
mA
mA
V
V
V
V
Note:
1. I
CC
in the erase mode is 50 mA.
5
京公网安备 11010802033920号
EEWORLD
