AT49BV1604AT datasheet, PDF - EEWORLD Datasheet

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AT49BV1604AT: Description1M X 16 FLASH 3V PROM, 70 ns, PBGA45; Categorystorage; File Size217KB，26 Pages; ManufacturerAtmel (Microchip)

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AT49BV1604AT Overview

1M X 16 FLASH 3V PROM, 70 ns, PBGA45

AT49BV1604AT Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	45
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	3.3 V
Minimum supply/operating voltage	2.65 V
Rated supply voltage	3 V
maximum access time	70 ns
Processing package description	6.50 × 7.50 MM, 1.20 MM HEIGHT, 0.75 MM PITCH, PLASTIC, CSBGA-45
state	DISCONTINUED
packaging shape	Rectangle
Package Size	GRID ARRAY, THIN PROFILE, FINE PITCH
surface mount	Yes
Terminal form	BALL
Terminal spacing	0.7500 mm
terminal coating	NOT SPECIFIED
Terminal location	BOTTOM
Packaging Materials	Plastic/Epoxy
Temperature level	INDUSTRIAL
memory width	16
organize	1M × 16
storage density	1.68E7 deg
operating mode	ASYNCHRONOUS
Number of digits	1.05E6 words
Number of digits	1M
Spare memory width	8
Memory IC type	FLASH 3V programmable read-only memory
serial parallel	parallel

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Features

•

Single Voltage Read/Write Operation: 2.65V to 3.3V (BV), 3.0V to 3.6V (LV)

•

Access Time – 70 ns

•

Sector Erase Architecture

•

– Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout

– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout

Fast Word Program Time – 20 µs

Fast Sector Erase Time – 300 ms

Dual-plane Organization, Permitting Concurrent Read while Program/Erase

Memory Plane A: Eight 4K Word and Seven 32K Word Sectors

Memory Plane B: Twenty-four 32K Word Sectors

Erase Suspend Capability

– Supports Reading/Programming Data from Any Sector by Suspending Erase of

Any Different Sector

Low-power Operation

– 30 mA Active

– 10 µA Standby

Data Polling, Toggle Bit, Ready/Busy for End of Program Detection

VPP Pin for Accelerated Program/Erase Operations

RESET Input for Device Initialization

Sector Lockdown Support

TSOP and CBGA Package Options

Top or Bottom Boot Block Configuration Available

128-bit Protection Register

16-megabit

(1M x 16/2M x 8)

3-volt Only

Flash Memory

AT49BV1604A

AT49BV1604AT

AT49BV1614A

AT49LV1614A

AT49BV1614AT

AT49LV1614AT

Description

The AT49BV/LV16X4A(T) is a 2.65- to 3.3-volt 16-megabit Flash memory organized

as 1,048,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data

appears on I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided

into 39 sectors for erase operations. The device is offered in 48-lead TSOP and

48-ball CBGA packages. The device has CE and OE control signals to avoid any bus

contention. This device can be read or reprogrammed using a single 2.65V power

supply, making it ideally suited for in-system programming.

Pin Configurations

Pin Name

A0 - A19

RESET

RDY/BUSY

VPP

I/O0 - I/O14

I/O15 (A-1)

BYTE

VCCQ

Function

Addresses

Chip Enable

Output Enable

Write Enable

Reset

READY/BUSY Output

Power Supply for Accelerated Program/Erase Operations

Data Inputs/Outputs

I/O15 (Data Input/Output, Word Mode) A-1 (LSB Address Input, Byte Mode)

Selects Byte or Word Mode

No Connect

Output Power Supply

Rev. 1411F–FLASH–03/02

AT49BV1604A(T)/1614A(T)

The device powers on in the read mode. Command sequences are used to place the device in

other operation modes such as program and erase. The device has the capability to protect

the data in any sector (see Sector Lockdown section).

The device is segmented into two memory planes. Reads from memory plane B may be per-

formed even while program or erase functions are being executed in memory plane A and vice

versa. This operation allows improved system performance by not requiring the system to wait

for a program or erase operation to complete before a read is performed. To further increase

the flexibility of the device, it contains an Erase Suspend feature. This feature will put the

erase on hold for any amount of time and let the user read data from or program data to any of

the remaining sectors within the same memory plane. There is no reason to suspend the

erase operation if the data to be read is in the other memory plane. The end of a program or

an erase cycle is detected by the Ready/Busy pin, Data Polling or by the toggle bit.

The VPP pin provides faster program/erase times. With V

at 5.0V or 12.0V, the program and

erase operations are accelerated.

A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement

of entering the three-byte program sequence is offered to further improve programming time.

After entering the six-byte code, only single pulses on the write control lines are required for

writing into the device. This mode (Single Pulse Byte/Word Program) is exited by powering

down the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing

it back to V

. Erase and Erase Suspend/Resume commands will not work while in this mode;

if entered they will result in data being programmed into the device. It is not recommended that

the six-byte code reside in the software of the final product but only exist in external program-

ming code.

When using the AT49BV1604A(T) pinout configuration, the device always operates in the

word mode. In the AT49BV/LV1614A(T) configuration, the BYTE pin controls whether the

device data I/O pins operate in the byte or word configuration. If the BYTE pin is set at logic

“1”, the device is in word configuration, I/O0 - I/O15 are active and controlled by CE and OE.

If the BYTE pin is set at logic “0”, the device is in byte configuration, and only data I/O pins

I/O0 - I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14 are tri-

stated, and the I/O15 pin is used as an input for the LSB (A-1) address function.

1411F–FLASH–03/02

AT49BV1604A(T)/1614A(T)

Device

Operation

READ:

The AT49BV/LV16X4A(T) is accessed like an EPROM. When CE and OE are low and

WE is high, the data stored at the memory location determined by the address pins are

asserted on the outputs. The outputs are put in the high-impedance state whenever CE or OE

is high. This dual-line control gives designers flexibility in preventing bus contention.

COMMAND SEQUENCES:

When the device is first powered on it will be reset to the read or

standby mode, depending upon the state of the control line inputs. In order to perform other

device functions, a series of command sequences are entered into the device. The command

sequences are shown in the Command Definitions table (I/O8 - I/O15 are don’t care inputs for

the command codes). The command sequences are written by applying a low pulse on the

WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the

falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of

CE or WE. Standard microprocessor write timings are used. The address locations used in the

command sequences are not affected by entering the command sequences.

RESET:

A RESET input pin is provided to ease some system applications. When RESET is at

a logic high level, the device is in its standard operating mode. A low level on the RESET input

halts the present device operation and puts the outputs of the device in a high-impedance

state. When a high level is reasserted on the RESET pin, the device returns to the read or

standby mode, depending upon the state of the control inputs.

ERASURE:

Before a byte/word can be reprogrammed, it must be erased. The erased state of

memory bits is a logical “1”. The entire device can be erased by using the Chip Erase com-

mand or individual sectors can be erased by using the Sector Erase command.

CHIP ERASE:

The entire device can be erased at one time by using the six-byte chip erase

software code. After the chip erase has been initiated, the device will internally time the erase

operation so that no external clocks are required. The maximum time to erase the chip is t

If the sector lockdown has been enabled, the chip erase will not erase the data in the sector

that has been locked out; it will erase only the unprotected sectors. After the chip erase, the

device will return to the read or standby mode.

SECTOR ERASE:

As an alternative to a full chip erase, the device is organized into 39 sec-

tors (SA0 - SA38) that can be individually erased. The Sector Erase command is a six-bus

cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while

the 30H data input command is latched on the rising edge of WE. The sector erase starts after

the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will

automatically time to completion. The maximum time to erase a section is t

SEC

. When the sec-

tor programming lockdown feature is not enabled, the sector will erase (from the same Sector

Erase command). An attempt to erase a sector that has been protected will result in the oper-

ation terminating in 2 µs.

BYTE/WORD PROGRAMMING:

Once a memory block is erased, it is programmed (to a logi-

cal “0”) on a byte-by-byte or on a word-by-word basis. Programming is accomplished via the

internal device command register and is a four-bus cycle operation. The device will automati-

cally generate the required internal program pulses.

Any commands written to the chip during the embedded programming cycle will be ignored. If

a hardware reset happens during programming, the data at the location being programmed

will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase

operations can convert “0”s to “1”s. Programming is completed after the specified t

cycle

time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a

program cycle.

VPP PIN:

The circuitry of the AT49BV/LV16X4A(T) is designed so that the device can be pro-

grammed or erased from the V

power supply or from the VPP input pin. When V

is less

than or equal to the VCC pin, the device selects the V

supply for programming and erase

1411F–FLASH–03/02

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