Preliminary
GS8160E18/32/36AT-300/275/250/225/200
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline
operation
• Dual Cycle Deselect (DCD) operation
• 1.8 V or 2.5 V +10%/–10% core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
-300 -275 -250 -225 -200 Unit
2.2 2.4 2.5 2.7 3.0 ns
3.3 3.6 4.0 4.4 5.0 ns
320
375
320
370
5.0
5.0
220
265
220
265
300
345
300
340
5.25
5.25
215
260
215
260
275
320
275
315
5.5
5.5
210
245
210
245
250
295
250
285
6.0
6.0
200
235
200
235
230
265
225
260
6.5
6.5
190
225
190
225
mA
mA
mA
mA
ns
ns
mA
mA
mA
mA
1M x 18, 512K x 32, 512K x 36
18Mb Sync Burst SRAMs
300 MHz–200 MHz
1.8 V or 2.5 V V
DD
1.8 V or 2.5 V I/O
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode pin
low places the RAM in Flow Through mode, causing output
data to bypass the Data Output Register. Holding FT high
places the RAM in Pipeline mode, activating the rising-edge-
triggered Data Output Register.
Pipeline
3-1-1-1
2.5 V
1.8 V
Flow
Through
2-1-1-1
2.5 V
1.8 V
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
Curr
(x18)
Curr
(x32/x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
Curr
(x18)
Curr
(x32/x36)
DCD Pipelined Reads
The GS8160E18/32/36AT is a DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. SCD (Single Cycle Deselect)
versions are also available. DCD SRAMs pipeline disable
commands to the same degree as read commands. DCD RAMs
hold the deselect command for one full cycle and then begin
turning off their outputs just after the second rising edge of
clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Functional Description
Applications
The GS8160E18/32/36AT is a 18,874,368-bit (16,777,216-bit
for x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8160E18/32/36AT operates on a 1.8 V or 2.5 V power
supply. All inputs are 2.5 V and 1.8 V compatible. Separate
output power (V
DDQ
) pins are used to decouple output noise
from the internal circuits and are 2.5 V and 1.8 V compatible.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
Rev: 1.02a 9/2002
1/26
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160E18/32/36AT-300/275/250/225/200
TQFP Pin Description
Symbol
A
0
, A
1
A
2
–A
18
A
19
DQ
A1
–DQ
A9
DQ
B1
–DQ
B9
DQ
C1
–DQ
C9
DQ
D1
–DQ
D9
NC
BW
B
A
, B
B,
B
C
, B
D
CK
GW
E
1
, E
3
E
2
G
ADV
ADSP, ADSC
ZZ
FT
LBO
V
DD
V
SS
V
DDQ
NC
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
—
Type
I
I
I
I/O
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Address Inputs
Data Input and Output pins
No Connect
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
No Connect
Rev: 1.02a 9/2002
5/26
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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