GS8256436GD-250IVT datasheet, PDF

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GS8256436GD-250IVT: DescriptionCache SRAM, 8MX36, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165; Categorystorage storage; File Size581KB，32 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS8256436GD-250IVT Overview

Cache SRAM, 8MX36, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

GS8256436GD-250IVT Parametric

Parameter Name	Attribute value
Maker	GSI Technology
package instruction	LBGA,
Reach Compliance Code	compli
ECCN code	3A991.B.2.B
Other features	IT ALSO OPERATES AT 2.3 V TO 2.7 V SUPPLY VOLTAGE
JESD-30 code	R-PBGA-B165
length	15 mm
memory density	301989888 bi
Memory IC Type	CACHE SRAM
memory width	36
Number of functions	1
Number of terminals	165
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
organize	8MX36
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Maximum seat height	1.5 mm
Maximum supply voltage (Vsup)	2 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	13 mm

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Advanced Information

GS8256418/36(GB/GD)-xxxV

119- & 165-Bump BGA

Commercial Temp

Industrial Temp

Features

16M x 18, 8M x 36

288Mb DCD Sync Burst SRAMs

333 MHz–200 MHz

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 1.8 V +10%/–10% core power supply

• 2.5 V +10%/–10% core power supply

• 1.8 V or 2.5 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• ZZ pin for automatic power-down

• RoHS-compliant 119-bump and 165-bump BGA packages

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the

user via the FT mode . Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the

Data Output Register. Holding FT high places the RAM in

Pipeline mode, activating the rising-edge-triggered Data Output

DCD Pipelined Reads

The GS8256418/36-xxxV is a DCD (Dual Cycle Deselect)

pipelined synchronous SRAM. DCD SRAMs pipeline disable

commands to the same degree as read commands. DCD RAMs

hold the deselect command for one full cycle and then begin

turning off their outputs just after the second rising edge of clock.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ low)

for multi-drop bus applications and normal drive strength (ZQ

floating or high) point-to-point applications. See the Output Driver

Characteristics chart for details.

Core and Interface Voltages

The GS8256418/36-xxxV operates on a 1.8 V or 2.5 V power

supply. All input are 31.8 V or 2.5 V compatible. Separate output

Functional Description

Applications

The GS8256418/36-xxxV is a

301,989,888

-bit high performance

synchronous SRAM with a 2-bit burst address counter. Although

of a type originally developed for Level 2 Cache applications

supporting high performance CPUs, the device now finds

application in synchronous SRAM applications, ranging from

DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

Parameter Synopsis

tCycle

Curr

(x18)

Curr

(x36)

tCycle

Curr

(x18)

Curr

(x36)

-333

2.5

3.0

TBD

4.5

TBD

-250

2.5

4.0

TBD

5.5

TBD

-200

3.0

5.0

TBD

6.5

TBD

Unit

Pipeline

3-1-1-1

Flow Through

2-1-1-1

Rev: 1.01 8/2016

1/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8256436GD-250IVT Related Products

	GS8256436GD-250IVT	GS8256436GB-333IVT	GS8256436GB-200VT	GS8256436GB-200IVT	GS8256436GD-333V	GS8256436GD-200V	GS8256436GD-250V
Description	Cache SRAM, 8MX36, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165	Cache SRAM, 8MX36, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, ROHS COMPLIANT, FPBGA-119	Cache SRAM, 8MX36, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, ROHS COMPLIANT, FPBGA-119	Cache SRAM, 8MX36, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, ROHS COMPLIANT, FPBGA-119	Cache SRAM, 8MX36, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165	Cache SRAM, 8MX36, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165	Cache SRAM, 8MX36, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
package instruction	LBGA,	BGA,	BGA,	BGA,	LBGA,	LBGA,	LBGA,
Reach Compliance Code	compli	compliant	compliant	compliant	compliant	compli	compli
ECCN code	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B
Other features	IT ALSO OPERATES AT 2.3 V TO 2.7 V SUPPLY VOLTAGE	IT ALSO OPERATES AT 2.3 V TO 2.7 V SUPPLY VOLTAGE	IT ALSO OPERATES AT 2.3 V TO 2.7 V SUPPLY VOLTAGE	IT ALSO OPERATES AT 2.3 V TO 2.7 V SUPPLY VOLTAGE	IT ALSO OPERATES AT 2.3 V TO 2.7 V SUPPLY VOLTAGE	IT ALSO OPERATES AT 2.3 V TO 2.7 V SUPPLY VOLTAGE	IT ALSO OPERATES AT 2.3 V TO 2.7 V SUPPLY VOLTAGE
JESD-30 code	R-PBGA-B165	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165
length	15 mm	22 mm	22 mm	22 mm	15 mm	15 mm	15 mm
memory density	301989888 bi	301989888 bit	301989888 bit	301989888 bit	301989888 bit	301989888 bi	301989888 bi
Memory IC Type	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM
memory width	36	36	36	36	36	36	36
Number of functions	1	1	1	1	1	1	1
Number of terminals	165	119	119	119	165	165	165
word count	8388608 words	8388608 words	8388608 words	8388608 words	8388608 words	8388608 words	8388608 words
character code	8000000	8000000	8000000	8000000	8000000	8000000	8000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
organize	8MX36	8MX36	8MX36	8MX36	8MX36	8MX36	8MX36
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LBGA	BGA	BGA	BGA	LBGA	LBGA	LBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Maximum seat height	1.5 mm	1.99 mm	1.99 mm	1.99 mm	1.5 mm	1.5 mm	1.5 mm
Maximum supply voltage (Vsup)	2 V	2 V	2 V	2 V	2 V	2 V	2 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1.27 mm	1.27 mm	1.27 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	13 mm	14 mm	14 mm	14 mm	13 mm	13 mm	13 mm
Base Number Matches	-	1	1	1	1	-	-
Maximum operating temperature	-	-	85 °C	-	85 °C	85 °C	85 °C
Temperature level	-	-	OTHER	-	OTHER	OTHER	OTHER

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