IS25LQ080
8M-BIT
3V- QUAD SERIAL FLASH MEMORY MULTI- I/O SPI
FEATURES
Industry Standard Serial Interface
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IS25LQ080: 8M-bit/ 1M-byte
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256-bytes per Programmable Page Standard
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Standard SPI/ Dual SPI/ Quad SPI
High Performance Multi-I/O Serial Flash (SPI)
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104 MHz SPI/ Dual/ or Quad SPI
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416 MHz equivalent Quad SPI
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52MB/S Continuous Data Throughput
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Supports SPI Modes 0 and 3
(1)
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More than 100,000 erase/program cycles
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More than 20-year data retention
Efficient Read and Program modes
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Low Instruction Overhead Operations
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Continuous data read with Byte Wrap around
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Allows XIP operations (execute in place)
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Outperforms X16 Parallel Flash
Low Power with Wide Temp. Ranges
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Single 2.3V to 3.6V Voltage Supply
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10 mA Active Read Current
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5 µA Standby Current
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Temp Grades:
Extended: -40°C to +105°C
Auto Grade: up to +125°C (call factory)
Flexible & Cost Efficient Memory Architecture
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Uniform 4K-byte Sector Erase
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Uniform 64K-byte Block Erase
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Program from 1 to 256 bytes
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Program and Erase Suspend/Resume
GENERAL DESCRIPTION
N
O
The memory array is organized into programmable pages of 256-bytes each. The IS25LQ080 supports page
program mode where 1 to 256 bytes of data can be programmed into the memory with one command. Pages
can be erased in groups of 4K-byte sectors, 64K-byte blocks, and/or the entire chip. The uniform 4K-byte
sectors and 64K-byte blocks allow greater flexibility for a variety of applications requiring solid data retention.
The device supports the standard Serial Peripheral Interface (SPI), Dual/Quad output (SPI), and Dual/Quad I/O
(SPI). Clock frequencies of up to 104MHz for SPI, Dual, and Quad modes allow for equivalent clock rates of up
to 416MHz (104MHz x 4) allowing up to 52MB/S of throughput. These transfer rates can outperform 16-bit
Parallel Flash memories allowing for efficient memory access for a XIP (execute in place) operation.
The IS25LQ080 is manufactured using industry leading non-volatile memory technology. The devices are
offered in industry standard lead-free packages. See Ordering Information for the density and package
combinations available.
1.
100,000 Continuous Chip and Block cycling, 100,000 Continuous Sector cycling
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
2/7/2014
T
The IS25LQ080 (8M-bit) Serial Flash memory offers a storage solution with flexibility and performance in a
simplified pin count package. ISSI’s “Industry Standard Serial Interface” is for systems that have limited space,
pins, and power. The IS25LQ080 are accessed through a 4-wire SPI Interface consisting of a Serial Data Input
(Sl), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins, which also serve as multi-
function I/O pins in Dual and Quad modes (see pin descriptions). The IS25xQ series of flash is ideal for code
shadowing to RAM, execute in place (XIP) operations, and storing non-volatile data.
R
EL
EA
Advanced Security Protection
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Software and Hardware Write Protection
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64-Byte dedicated area, user-lockable, One
Time Programmable Memory (OTP)
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Safeguard- Single Sector lock and unlock
Industry Standard Pin-out & Pb-Free Packages
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JB = 8-pin SOIC 208mil
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JN = 8-pin SOIC 150mil
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JV = 8-pin VVSOP 150mil
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JK = 8-pin WSON 6x5mm
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KGD (call factory)
SE
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IS25LQ080
PIN DESCRIPTIONS
SYMBOL
TYPE
DESCRIPTION
Chip Enable:
The Chip Enable (CE#) pin enables and disables the devices
operation. When CE# is high the device is deselected and output pins are in a high
impedance state. When deselected the devices non-critical internal circuitries power
down to allow minimal levels of power consumption while in a standby state.
Keeping CE# in a high state deselects the device and switches it into its low power
state. Data will not be accepted when CE# is high.
SI (IO0),
SO (IO1)
INPUT/OUTPUT
This device supports standard SPI, Dual SPI, and Quad SPI operation. Standard SPI
instructions use the unidirectional SI (Serial Input) pin to write instructions,
addresses, or data to the device on the rising edge of the Serial Clock (SCK).
Standard SPI also uses the unidirectional SO (Serial Output) to read data or status
from the device on the falling edge of the serial clock (SCK).
In Dual and Quad SPI mode, SI and SO become bidirectional IO pins to write
instructions, addresses or data to the device on the rising edge of the Serial Clock
(SCK) and read data or status from the device on the falling edge of SCK. Quad SPI
instructions use the WP# and HOLD# pins as IO2 and IO3 respectively.
Write Protect:
The WP# pin protects the Status Register from being written. When
the WP# is low the status registers are write-protected and vice-versa for high. When
the QE bit is set to “1”, the WP# pin (Write Protect) function is not available since this
pin is used for IO2.
Hold:
Pauses serial communication by the master device without resetting the serial
sequence. When the QE bit of Status Register is set to “1”, HOLD# pin is not
available since it becomes IO3.
The HOLD# pin allows the device to be paused while it is selected. The HOLD# pin
is active low. When HOLD# is in a low state, and CE# is low, the SO pin will be at
high impedance.
Device operation can resume when HOLD# pin is brought to a high state. When the
QE bit of Status Register is set for Quad I/O, the HOLD# pin function is not available
and becomes IO3 for Multi-I/O SPI mode.
Serial Data Clock:
Synchronized Clock for input and output timing operations.
Power:
Device Core Power Supply
Ground:
Connect to ground when referenced to Vcc
NC:
Pins labeled “NC” stand for “No Connect” and should be left uncommitted.
WP# (IO2)
INPUT/OUTPUT
N
O
SCK
Vcc
GND
NC
Table 1. Pin Descriptions
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
2/7/2014
T
HOLD# (IO3)
R
INPUT/OUTPUT
INPUT
POWER
GROUND
Unused
EL
EA
Serial Data Input, Serial Output, and IOs (SI, SO, IO0, and IO1):
SE
CE#
INPUT
When CE# is pulled low the device will be selected and brought out of standby
mode. The device is considered active and instructions can be written to, data read,
and written to the device. After power-up, CE# must transition from high to low
before a new instruction will be accepted.
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