MOBILE PENTIUM® PROCESSOR WITH
MMX™ TECHNOLOGY ON 0.25 MICRON
Operating Frequency
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166 MHz
200 MHz
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233 MHz
266 MHz
Advanced Design Features
Deeper Write Buffers
Enhanced Branch Prediction Feature
Virtual Mode Extensions
0.25 Micron Process Technology
1.8 V core supply (166/200/233 MHz)
2.0 V core supply (266 MHz)
2.5 V I/O Interface (166/200/233/266 MHz
)
Internal Error Detection Features
On-Chip Local APIC Controller
Power Management Features
System Management Mode
Clock Control
Fractional Bus Operation
166-MHz Core/66-MHz Bus
200-MHz Core/66-MHz Bus
233-MHz Core/66-MHz Bus
266-MHz Core/66-MHz Bus
Support for MMX™ Technology
Compatible with Large Software Base
MS-DOS*, Windows*, OS/2*, UNIX*
32-Bit CPU with 64-Bit Data Bus
Superscalar Architecture
Enhanced pipelines
Two Pipelined Integer Units Capable of 2
Instructions/Clock
Pipelined MMX Technology
Pipelined Floating-Point Unit
Separate Code and Data Caches
16-Kbyte Code, 16-Kbyte Write Back
Data
MESI Cache Protocol
4-Mbyte Pages for Increased TLB Hit Rate
320-pin TCP or Mobile Module
IEEE 1149.1 Boundary Scan
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The mobile Pentium
®
processor with MMX™ technology on 0.25 micron
extends the mobile Pentium
processor family, providing additional performance for notebook applications. The mobile Pentium processor
with MMX technology on 0.25 micron is compatible with the entire installed base of applications for MS-
DOS*, Windows*, OS/2*, and UNIX* and is one of the major microprocessors to support Intel MMX
technology. Furthermore, the mobile Pentium processor with MMX technology on 0.25 micron has
superscalar architecture which can execute two instructions per clock cycle, and enhanced branch prediction
and separate caches also increase performance. The pipelined floating-point unit delivers workstation level
performance. Separate code and data caches reduce cache conflicts while remaining software transparent.
The mobile Pentium processor with MMX technology on 0.25 micron has 4.5 million transistors, is built on
Intel's 0.25 micron manufacturing process technology and has full SL Enhanced power management features
including System Management Mode (SMM) and clock control. The additional SL Enhanced features,
1.8/2.0V core operation along with 2.5V I/O buffer operation, a 320-pin Tape Carrier Package (TCP), and the
Intel mobile module, make the mobile Pentium processor with MMX technology on 0.25 micron ideal for
enabling mobile MMX technology designs. The mobile Pentium processor with MMX technology on 0.25
micron may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available upon request.
January 1998
Order Number: 243468-002
MOBILE PENTIUM
®
PROCESSOR WITH MMX™ TECHNOLOGY
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’ Terms and Conditions of
s
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from
future changes to them.
Intel may make changes to specifications and product descriptions at any time, without notice.
The mobile Pentium® processor with MMX™ technology may contain design defects or errors known as errata which may
cause the product to deviate from published specifications. Current characterized errata are available on request.
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CODECs, or MPEG enabled platforms may require licenses from various entities, including Intel Corporation.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained by calling 1-800-548-4725 or by visiting Intel’ website at http://www.intel.com
s
Copyright © Intel Corporation1997. Third-party brands and names are the property of their respective owners.
2
MOBILE PENTIUM
®
PROCESSOR WITH MMX™ TECHNOLOGY
CONTENTS
PAGE
1.0. INTRODUCTION ............................................ 4
2.0. MICROPROCESSOR ARCHITECTURE
OVERVIEW .................................................... 4
2.1. Mobile Pentium ® Processor Family
Architecture ................................................ 5
2.2. Mobile Pentium ® Processor with MMX
TM
Technology ................................................. 7
2.2.1. Full support for Intel MMX
TM
technology ........................................... 7
2.2.2. Doubled code and data caches to 16K
each..................................................... 7
2.2.3. Improved branch prediction .................. 7
2.2.4. Enhanced pipeline ................................ 8
2.3 0.25 Micron Technology.… … … … … … … ..8
3.0. MOBILE PENTIUM ® PROCESSOR WITH
MMX™ TECHNOLOGY PINOUT ................... 8
3.1. Mobile Differences from Desktop ................ 8
3.2. TCP Pinout and Pin Descriptions ................ 9
3.2.1. TCP MOBILE PENTIUM ®
PROCESSOR WITH MMX™
TECHNOLOGY PINOUT ..................... 9
3.2.2. TCP MOBILE PENTIUM ®
PROCESSOR WITH MMX™
TECHNOLOGY PIN CROSS
REFERENCE ..................................... 10
3.3. Design Notes ............................................ 17
3.4. Quick Pin Reference ................................. 17
3.5. Bus Frequency ......................................... 26
3.6. Pin Reference Tables ............................... 27
PAGE
3.7. Pin Grouping According to Function .......... 30
4.0. ELECTRICAL SPECIFICATIONS ................ 31
4.1. Maximum Ratings ..................................... 31
4.2. DC Specifications ...................................... 31
4.2.1. POWER SEQUENCING ..................... 31
4.3. AC Specifications ...................................... 34
4.3.1. POWER AND GROUND .................... 34
4.3.2. DECOUPLING RECOMMENDATION 34
4.3.3. CONNECTION SPECIFICATIONS ..... 35
4.3.4. AC TIMINGS FOR A 66-MHZ BUS .... 35
4.4. I/O Buffer Models ...................................... 46
4.4.1. BUFFER MODEL PARAMETERS ...... 49
4.4.2. SIGNAL QUALITY SPECIFICATION .. 51
4.4.3. CLOCK SIGNAL MEASUREMENT
METHODOLOGY ............................... 55
5.0. MECHANICAL SPECIFICATIONS ............... 57
5.1. TCP Mechanical Diagrams ....................... 58
6.0. THERMAL SPECIFICATIONS ..................... 64
6.1. Measuring Thermal Values for TCP .......... 64
6.1.1. TCP Thermal Equations ..................... 64
6.1.2. TCP Thermal Characteristics ............. 64
6.1.3. TCP PC Board Enhancements ........... 64
6.1.3.1. TCP STANDARD TEST BOARD
CONFIGURATION ............................. 65
3
MOBILE PENTIUM
®
PROCESSOR WITH MMX™ TECHNOLOGY
2.0.
1.0.
INTRODUCTION
MICROPROCESSOR
ARCHITECTURE OVERVIEW
The mobile Pentium® processors with MMX™
technology on 0.25 micron
are fully compatible
with the existing mobile Pentium processors with
MMX technology (120, 133, 150, & 166 MHz) with
the following differences: voltage supplies, power
consumption,
and
performance.
These
processors, when used in a TCP package, are
socket compatible with the mobile Pentium
processor (75, 90, 100, 120, 133, 150 MHz)
making it possible to design a flexible motherboard
that supports both the mobile Pentium processor
(75 MHz - 150 MHz) and the mobile Pentium
processor with MMX technology (120
MHz - 266
MHz). It has all the advanced features of the
desktop version of the Pentium processor with
MMX technology except for the differences listed
in Section 3.1.
The mobile Pentium processor with MMX
technology on 0.25 micron
has several features
which allow high-performance notebooks to be
designed, including the following:
•
•
•
TCP dimensions are ideal for small form-factor
designs.
TCP has superior thermal resistance
characteristics.
1.8V (166/200/233 MHz)/2.0V (266 MHz)
core
and 2.5V I/O buffer V
CC
inputs reduce power
consumption significantly.
The SL Enhanced feature set.
The mobile Pentium processor with MMX
technology on 0.25 micron
extends the mobile
Pentium processor with MMX technology family. It
is binary compatible with the 8086/88™ , 80286™ ,
Intel386™ DX, Intel386 SX, Intel486™ DX,
Intel486 SX, Intel486 DX2, and mobile Pentium
processors with voltage reduction technology (75-
150).
The mobile Pentium processor family consists of
the mobile Pentium processor with MMX
technology (120,
133, 150, & 166), The mobile
Pentium processor with MMX technology on 0.25
micron (166, 200, 233, & 266)
and the mobile
Pentium processor with voltage reduction
technology (75 MHz -150 MHz).
The mobile Pentium processor with MMX
technology
on 0.25 micron
contains all of the
features of previous Intel Architecture and
provides significant enhancements and additions
including the following:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Support for MMX™ Technology
Superscalar Architecture
Enhanced Branch Prediction Algorithm
Pipelined Floating-Point Unit
Improved Instruction Execution Time
Separate 16K Code and 16K Data Caches
Writeback MESI Protocol in the Data Cache
64-Bit Data Bus
Enhanced Bus Cycle Pipelining
Address Parity
Internal Parity Checking
Execution Tracing
Performance Monitoring
IEEE 1149.1 Boundary Scan
System Management Mode
Virtual Mode Extensions
0.25 Micron Process
Technology
SL Power Management Features
Pool of four write buffers used by both pipes
•
The architecture and internal features of the
mobile Pentium processor with MMX technology
on 0.25 micron
are identical to the desktop version
specifications provided in the
Pentium
®
Processor
Family Developer’ Manual
(Order Number
s
241428), except several features not used in
mobile applications which have been eliminated to
streamline it for mobile applications.
This document should be used in conjunction with
Pentium
®
Processor Family Developer’ Manual
s
(Order Number: 241428)
4
MOBILE PENTIUM
®
PROCESSOR WITH MMX™ TECHNOLOGY
2.1.
Mobile Pentium
®
Processor
Family Architecture
The application instruction set of the mobile
Pentium processor family includes the complete
Intel486 CPU family instruction set with extensions
to accommodate some of the additional
functionality of the Pentium processors. All
application software written for the Intel386 and
Intel486 family microprocessors will run on the
Pentium processors without modification. The on-
chip memory management unit (MMU) is
completely compatible with the Intel386 and
Intel486 families of processors.
The Pentium processors implement several
enhancements to increase performance. The two
instruction pipelines and floating-point unit on
Pentium processors are capable of independent
operation. Each pipeline issues frequently used
instructions in a single clock. Together, the dual
pipes can issue two integer instructions in one
clock, or one floating-point instruction (under
certain
circumstances,
two
floating-point
instructions) in one clock.
Branch prediction is implemented in the Pentium
processors. To support this, Pentium processors
implement two prefetch buffers, one to prefetch
code in a linear fashion, and one that prefetches
code according to the Branch Target Buffer (BTB)
so the needed code is almost always prefetched
before it is needed for execution.
The floating-point unit has been completely
redesigned over the Intel486 processor. Faster
algorithms provide up to 10X speed-up for
common operations including add, multiply and
load.
Pentium processors include separate code and
data caches integrated on-chip to meet
performance goals. Each cache has a 32-byte line
size and is 4-way set associative. Each cache has
a dedicated Translation Lookaside Buffer (TLB) to
translate linear addresses to physical addresses.
The data cache is configurable to be writeback or
writethrough on a line-by-line basis and follows the
MESI protocol. The data cache tags are triple
ported to support two data transfers and an inquire
cycle in the same clock. The code cache is an
inherently write-protected cache. The code cache
tags are also triple ported to support snooping and
split line accesses. Individual pages can be
configured as cacheable or non-cacheable by
software or hardware. The caches can be enabled
or disabled by software or hardware.
The Pentium processors have increased the data
bus to 64 bits to improve the data transfer rate.
Burst read and burst writeback cycles are
supported by the Pentium processors. In addition,
bus cycle pipelining has been added to allow two
bus cycles to be in progress simultaneously. The
Pentium processors' MMU contains optional
extensions to the architecture which allow 4-Kbyte
and 4-Mbyte page sizes.
The Pentium processors have added significant
data integrity and error detection capability. Data
parity checking is still supported on a byte-by-byte
basis. Address parity checking and internal parity
checking features have been added along with a
new exception, the machine check exception.
As more and more functions are integrated on
chip, the complexity of board level testing is
increased. To address this, the Pentium
processors have increased test and debug
capability. The Pentium processors implement
IEEE Boundary Scan (Standard 1149.1). In
addition, the Pentium processors have specified
four breakpoint pins that correspond to each of the
debug registers and externally indicate a
breakpoint match. Execution tracing provides
external indications when an instruction has
completed execution in either of the two internal
pipelines, or when a branch has been taken.
System Management Mode (SMM) has been
implemented along with some extensions to the
SMM architecture. Enhancements to the virtual
8086 mode have been made to increase
performance by reducing the number of times it is
necessary to trap to a vir tual 8086 monitor.
Figure 1 shows a block diagram of the mobile
Pentium processor with MMX technology.
The block diagram shows the two instruction
pipelines, the "u" pipe and "v" pipe. The u-pipe can
execute all integer and floating-point instructions.
The v-pipe can execute simple integer instructions
and the FXCH floating-point instructions.
5
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