Features
•
Single Voltage Operation
•
•
•
•
•
•
•
•
•
– 5V Read
– 5V Reprogramming
Fast Read Access Time - 45 ns
Internal Program Control and Timer
8K word Boot Block With Lockout
Fast Erase Cycle Time - 10 seconds
Word By Word Programming - 10
µ
s/Word Typical
Hardware Data Protection
DATA Polling For End Of Program Detection
Small 10 x 14 mm VSOP Package
Typical 10,000 Write Cycles
Description
The AT49F1024 and the AT49F1025 are 5-volt-only in-system Flash Memories. Their
1 megabit of memory is organized as 65,536 words by 16 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 45
ns with power dissipation of just 275 mW over the commercial temperature range.
When the device is deselected, the CMOS standby current is less than 100
µA.
The
only difference between the AT49F1024 and the AT49F1025 is the pinout. The
AT49F1024 is pin compatable with the AT27C1024, and the AT49F1025 is pin com-
patable with the AT29C1024.
(continued)
1-Megabit
(64K x 16)
5-volt Only
Flash Memory
AT49F1024
AT49F1025
Pin Configurations
Pin Name
A0 - A15
CE
OE
WE
I/O0 - I/O15
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
AT49F1025 VSOP Top View
Type 1
10 x 14 mm
A0
A1
A2
A3
A4
A5
A6
A7
A8
GND
A9
A10
A11
A12
A13
A14
A15
NC
WE
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/07
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
NC
CE
A9
A10
A11
A12
A13
A14
A15
NC
WE
VCC
NC
CE
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
AT49F1024 VSOP Top View
Type 1
10 x 14 mm
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
PLCC Top View
I/O13
I/O14
I/O15
CE
NC
NC
VCC
WE
NC
A15
A14
I/O12
I/O11
I/O10
I/O9
I/O8
GND
NC
I/O7
I/O6
I/O5
I/O4
7
8
9
10
11
12
13
14
15
16
17
6
5
4
3
2
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
10 x 14 mm
I/O3
I/O2
I/O1
I/O0
OE
DC
A0
A1
A2
A3
A4
18
19
20
21
22
23
24
25
26
27
28
Rev. 0765D–09/98
1
To allow for simple in-system reprogrammability, the
AT49F1024/1025 does not require high input voltages for
programming. Five-volt-only commands determine the read
and programming operation of the device. Reading data
out of the device is similar to reading from an EPROM.
Reprogramming the AT49F1024/1025 is performed by
erasing a block of data (entire chip or main memory block)
and then programming on a word by word basis. The typi-
cal word programming time is a fast 10
µs.
The end of a
program cycle can be optionally detected by the DATA poll-
ing feature. Once the end of a byte program cycle has been
detected, a new access for a read or program can begin.
The typical number of program and erase cycles is in
excess of 10,000 cycles.
The optional 8K words boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being erased or reprogrammed.
Block Diagram
V
CC
GND
OE
WE
CE
DATA INPUTS/OUTPUTS
I/O15 - I/O0
16
OE, CE, AND WE
LOGIC
DATA LATCH
INPUT/OUTPUT
BUFFERS
Y-GATING
MAIN MEMORY
(56K WORDS)
1FFFH
OPTIONAL BOOT
BLOCK (8K WORDS)
0000H
Y DECODER
ADDRESS
INPUTS
X DECODER
Device Operation
READ:
The AT49F1024/1025 is accessed like an
EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the
address pins is asserted on the outputs. The outputs are
put in the high impedance state whenever CE or OE is
high. This dual-line control gives designers flexibility in pre-
venting bus contention.
CHIP ERASE:
When the boot block programming lockout
feature is not enabled, the boot block and the main memory
block will erase together from the same chip erase com-
mand (See command definitions table). If the boot block
lockout function has been enabled, data in the boot section
will not be erased. However, data in the main memory sec-
tion will be erased. After a chip erase, the device will return
to the read mode.
MAIN MEMORY ERASE:
As an alternative to the chip
erase, a main memory block erase can be performed which
will erase all bytes not located in the boot block region to an
FFH. Data located in the boot region will not be changed
during a main memory block erase. The Main Memory
Erase command is a six bus cycle operation. The address
(5555H) is latched on the falling edge of the sixth cycle
while the 30H data input is latched on the rising edge of
WE. The main memory erase starts after the rising edge of
WE of the sixth cycle. Please see Main Memory Erase
cycle waveforms. The Main Memory Erase operation is
internally controlled; it will automatically time to completion.
WORD PROGRAMMING:
Once the memory array is
erased, the device is programmed (to a logical “0”) on a
word-by-word basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified t
BP
cycle
time. The DATA polling feature may also be used to indi-
cate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT:
The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
2
AT49F1024/1025
AT49F1024/1025
size of the block is 8K words. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block’s usage as a write protected region is
optional to the user. The address range of the boot block is
0000H to 1FFFH.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular pro-
gramming method and can be erased using either the chip
erase or the main memory block erase command. To acti-
vate the lockout feature, a series of six program commands
to specific addresses with specific data must be performed.
Please refer to the Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION:
A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 0002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lock-
out feature has been activated and the block cannot be
programmed. The software product identification exit code
should be used to return to standard operation.
PRODUCT IDENTIFICATION:
The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING:
The AT49F1024/1025 features DATA
polling to indicate the end of a program or erase cycle.
During a program cycle an attempted read of the last byte
loaded will result in the complement of the loaded data on
I/O7. Once the program cycle has been completed, true
data is valid on all outputs and the next cycle may begin.
DATA polling may begin at any time during the program
cycle.
TOGGLE BIT:
In addition to DATA polling the
AT49F1024/1025 provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from the
device will result in I/O6 toggling between one and zero.
Once the program cycle has completed, I/O6 will stop tog-
gling and valid data will be read. Examining the toggle bit
may begin at any time during a program cycle.
HARDWARE DATA PROTECTION:
Hardware features
protect against inadvertent programs to the
AT49F1024/1025 in the following ways: (a) V
CC
sense: if
V
CC
is below 3.8V (typical), the program function is inhib-
ited. (b) Program inhibit: holding any one of OE low, CE
high or WE high inhibits program cycles. (c) Noise filter:
Pulses of less than 15 ns (typical) on the WE or CE inputs
will not initiate a program cycle.
3
Command Definition (in Hex)
Command
Sequence
Read
Chip Erase
Main Memory Erase
Word Program
Boot Block Lockout
(2)
Product ID Entry
Product ID Exit
(3)
Bus
Cycles
1
6
6
4
6
3
3
1st Bus
Cycle
Addr
Addr
5555
5555
5555
5555
5555
5555
Data
D
OUT
AA
AA
AA
AA
AA
AA
2AAA
2AAA
2AAA
2AAA
2AAA
2AAA
55
55
55
55
55
55
5555
5555
5555
5555
5555
5555
80
80
A0
80
90
F0
5555
5555
Addr
5555
AA
AA
D
IN
AA
2AAA
55
5555
40
2AAA
2AAA
55
55
5555
5555
10
30
2nd Bus
Cycle
Addr
Data
3rd Bus
Cycle
Addr
Data
4th Bus
Cycle
Addr
Data
5th Bus
Cycle
Addr
Data
6th Bus
Cycle
Addr
Data
Product ID Exit
(3)
1
xxxx
F0
Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).
2. The 8K word boot sector has the address range 00000H to 1FFFH.
3. Either one of the Product ID Exit commands can be used.
Absolute Maximum Ratings*
Temperature Under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
CC
+ 0.6V
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
4
AT49F1024/1025
AT49F1024/1025
DCand AC Operating Range
AT49F1024/1025-45
Operating
Temperature (Case)
V
CC
Power Supply
Com.
Ind.
5V
±
10%
0°C - 70°C
AT49F1024/1025-55
0°C - 70°C
-40°C - 85°C
5V
±
10%
AT49F1024/1025-70
0°C - 70°C
-40°C - 85°C
5V
±
10%
AT49F1024/1025-90
0°C - 70°C
-40°C - 85°C
5V
±
10%
Operating Modes
Mode
Read
Program
(2)
Standby/Write Inhibit
Program Inhibit
Program Inhibit
Output Disable
Product Identification
A1 - A15 = V
IL
, A9 = V
H
,
(3)
A0 = V
IL
A1 - A15 = V
IL
, A9 = V
H
,
(3)
A0 = V
IH
A0 = V
IL
, A1 - A15 = V
IL
A0 = V
IH
, A1 - A15 = V
IL
Manufacturer Code
(4)
Device Code
(4)
Manufacturer Code
(4)
Device Code
(4)
CE
V
IL
V
IL
V
IH
X
X
X
OE
V
IL
V
IH
X
(1)
X
V
IL
V
IH
WE
V
IH
V
IL
X
V
IH
X
X
High Z
Ai
Ai
Ai
X
I/O
D
OUT
D
IN
High Z
Hardware
V
IL
V
IL
V
IH
Software
(5)
Notes:
1. X can be V
IL
or V
IH
.
2. Refer to AC Programming Waveforms.
3. V
H
= 12.0V
±
0.5V.
4. Manufacturer Code: 1FH, Device Code: 87H.
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
I
LI
I
LO
I
SB1
I
SB2
I
CC (1)
V
IL
V
IH
V
OL
V
OH1
V
OH2
Parameter
Input Load Current
Output Leakage Current
V
CC
Standby Current CMOS
V
CC
Standby Current TTL
V
CC
Active Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output High Voltage CMOS
I
OL
= 2.1 mA
I
OH
= -400
µA
I
OH
= -100
µA;
V
CC
= 4.5V
2.4
4.2
2.0
0.45
Condition
V
IN
= 0V to V
CC
V
I/O
= 0V to V
CC
Com.
CE = V
CC
- 0.3V to V
CC
CE = 2.0V to V
CC
f = 5 MHz; I
OUT
= 0 mA
Ind.
Min
Max
10
10
100
300
3
50
0.8
Units
µA
µA
µA
µA
mA
mA
V
V
V
V
V
Note:
1. In the erase mode, I
CC
is 90 mA.
5
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