SPICE Device Model SUP80N15-20L
Vishay Siliconix
N-Channel 150-V (D-S) 175°C MOSFET
CHARACTERISTICS
•
N- and P-Channel Vertical DMOS
•
Macro Model (Subcircuit Model)
•
Level 3 MOS
•
Apply for both Linear and Switching Application
•
Accurate over the
−55
to 125°C Temperature Range
•
Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the
−55
to 125°C
temperature ranges under the pulsed 0 to 10V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to
model the gate charge characteristics while avoiding convergence
difficulties of the switched C
gd
model. All model parameter values
are optimized to provide a best fit to the measured electrical data
and are not intended as an exact physical interpretation of the
device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 72425
12-Jun-04
www.vishay.com
1
SPICE Device Model SUP80N15-20L
Vishay Siliconix
SPECIFICATIONS (T
J
= 25°C UNLESS OTHERWISE NOTED)
Parameter
Static
Gate Threshold Voltage
On-State Drain Current
a
V
GS(th)
I
D(on)
V
DS
= V
GS
, I
D
= 250
µA
V
DS
= 5 V, V
GS
= 10 V
V
GS
= 10 V, I
D
= 30 A
Drain-Source On-State Resistance
a
r
DS(on)
V
GS
= 10 V, I
D
= 30 A, T
J
= 125°C
V
GS
= 10 V, I
D
= 30 A, T
J
= 175°C
V
GS
= 4.5 V, I
D
= 20 A
Forward Transconductance
a
Forward Voltage
a
Symbol
Test Conditions
Simulated
Data
1.7
314
0.016
0.023
0.026
0.017
93
0.92
Measured
Data
Unit
V
A
0.016
Ω
g
fs
V
SD
V
DS
= 15 V, I
D
= 30 A
I
S
= 80 A, V
GS
= 0 V
S
1
V
Dynamic
b
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
c
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
c
6590
V
GS
= 0 V, V
DS
= 25 V, f = 1 MHz
510
320
114
V
DS
= 50 V, V
GS
= 10 V, I
D
= 80 A
21
33
176
V
DD
= 50 V, R
L
= 0.93
Ω
I
D
≅
80 A, V
GEN
= 10 V, R
G
= 2.5
Ω
43
43
49
6500
520
270
110
21
33
20
100
70
135
Ns
NC
Pf
Gate-Source Charge
c
Gate-Drain Charge
c
Turn-On Delay Time
Rise Time
c
t
d(on)
t
r
Turn-Off Delay Time
Fall Time
c
c
t
d(off)
t
f
Notes
a.
Pulse test; pulse width
≤
300
µs,
duty cycle
≤
2%.
b.
Guaranteed by design, not subject to production testing.
c.
Independent of operating temperature.
www.vishay.com
2
Document Number: 72425
12-Jun-04
FPGA/CPLD
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