L7C108/109
DEVICES INCORPORATED
128K x 8 Static RAM
L7C108/109
DEVICES INCORPORATED
128K x 8 Static RAM
DESCRIPTION
The
L7C108
and
L7C109
are high-
performance, low-power CMOS static
RAMs. The storage circuitry is organ-
ized as 131,072 words by 8 bits per
word. The 8 Data In and Data Out
signals share I/O pins. The L7C108 has
a single active-low Chip Enable. The
L7C109 has two Chip Enables (one
active-low). These devices are available
in three speeds with maximum access
times from 17 ns to 25 ns.
Inputs and outputs are TTL compat-
ible. Operation is from a single +5 V
power supply. Power consumption
is 550 mW (typical) at 25 ns. Dissipa-
tion drops to 50 mW (typical) when
the memory is deselected.
Two standby modes are available.
Proprietary Auto-Powerdown™
circuitry reduces power consumption
automatically during read or write
accesses which are longer than the
minimum access time, or when the
memory is deselected. In addition,
data may be retained in inactive
storage with a supply voltage as low
as 2 V. The L7C108 and L7C109
consume only 1.5 mW (typical), at 3 V,
allowing effective battery backup
operation.
The L7C108 and L7C109 provide
asynchronous (unclocked) operation
with matching access and cycle times.
The Chip Enables and a three-state I/O
bus with a separate Output Enable
control simplify the connection of
several chips for increased storage
capacity.
Memory locations are specified on
address pins A
0
through A
16
. For the
L7C108, reading from a designated
location is accomplished by presenting
an address and driving CE
1
and OE
LOW while WE remains HIGH. For
the L7C109, CE
1
and OE must be
LOW while CE
2
and WE are HIGH.
The data in the addressed memory
location will then appear on the Data
Out pins within one access time. The
output pins stay in a high-impedance
state when CE
1
or OE is HIGH, or CE
2
(L7C109) or WE is LOW.
Writing to an addressed location is
accomplished when the active-low
CE
1
and WE inputs are both LOW,
and CE
2
(L7C109) is HIGH. Any of
these signals may be used to terminate
the write operation. Data In and Data
Out signals have the same polarity.
Latchup and static discharge protection
are provided on-chip. The L7C108 and
L7C109 can withstand an injection
current of up to 200 mA on any pin
without damage.
FEATURES
q
128K x 8 Static RAM with Chip
Select Powerdown, Output Enable
q
Auto-Powerdown™ Design
q
Advanced CMOS Technology
q
High Speed — to 17 ns maximum
q
Low Power Operation
Active: 550 mW typical at 25 ns
Standby: 5 mW typical
q
Data Retention at 2 V for Battery
Backup Operation
q
DESC SMD No. 5962-89598
q
Available 100% Screened to
MIL-STD-883, Class B
q
Plug Compatible with Cypress
CY7C108/109, IDT71024/71B024,
Micron MT5C1008, Motorola
MCM6226A/62L26A, Sony
CXK581020
q
Package Styles Available:
• 32-pin Plastic DIP
• 32-pin Sidebraze, Hermetic DIP
• 32-pin Plastic SOJ
• 32-pin Ceramic SOJ
• 32-pin Ceramic LCC
1
2
3
4
5
6
7
8
9
10
11
L7C108/109 B
LOCK
D
IAGRAM
ROW SELECT
ROW
ADDRESS
9
512 x 256 x 8
MEMORY
ARRAY
CE
1
WE
OE
CE
2
(L7C109 only)
CONTROL
COLUMN SELECT
& COLUMN SENSE
8
COLUMN ADDRESS
8
I/O
7-0
1M Static RAMs
5-9
03/21/95–LDS.108/9-F
L7C108/109
DEVICES INCORPORATED
128K x 8 Static RAM
NOTES
1. Maximum Ratings indicate stress specifi-
cations only. Functional operation of these
products at values beyond those indicated
in the Operating Conditions table is not
implied. Exposure to maximum rating con-
ditions for extended periods may affect re-
liability of the tested device.
2. The products described by this specifica-
tion include internal circuitry designed to
protect the chip from damaging substrate
injection currents and accumulations of
static charge. Nevertheless, conventional
precautions should be observed during
storage, handling, and use of these circuits
in order to avoid exposure to excessive elec-
trical stress values.
3. This product provides hard clamping of
transient undershoot. Input levels below
ground will be clamped beginning at –0.6 V.
A current in excess of 100 mA is required to
reach –2.0 V. The device can withstand in-
definite operation with inputs as low as –3 V
subject only to power dissipation and bond
wire fusing constraints.
4. Tested with GND
≤
V
OUT
≤
V
CC
. The de-
vice is disabled, i.e., CE
1
=
V
CC
, CE
2
= GND.
5. A series of normalized curves is available
to supply the designer with typical DC and
AC parametric information for Logic Devices
Static RAMs. These curves may be used to
determine device characteristics at various
temperatures and voltage levels.
6. Tested with all address and data inputs
changing at the maximum cycle rate. The
device is continuously enabled for writing,
i.e., CE
1
≤
V
IL
, CE
2
≥
V
IH
, WE
≤
V
IL
. Input
pulse levels are 0 to 3.0 V.
7. Tested with outputs open and all address
and data inputs changing at the maximum
read cycle rate. The device is continuously
disabled, i.e., CE
1
≥
V
IH
, CE
2
≤
V
IL
.
8. Tested with outputs open and all ad-
dress and data inputs stable. The device
is continuously disabled, i.e., CE
1
=
V
CC
,
CE
2
= GND. Input levels are within 0.2 V
of
V
CC
or GND.
9. Data retention operation requires that
V
CC
never drop below 2.0 V. CE
1
must be
≥
V
CC
– 0.2 V or CE
2
must be
≤
0.2 V. All
other inputs must meet
V
IN
≥
V
CC
– 0.2 V or
V
IN
≤
0.2 V to ensure full powerdown. For
low power version (if applicable), this re-
quirement applies only to CE
1
, CE
2
, and
WE; there are no restrictions on data and
address.
10. These parameters are guaranteed but
not 100% tested.
11. Test conditions assume input transition
times of less than 3 ns, reference levels of
1.5 V, output loading for specified
I
OL
and
I
OH
plus 30 pF (Fig. 1a), and input pulse
levels of 0 to 3.0 V (Fig. 2).
12. Each parameter is shown as a minimum
or maximum value. Input requirements are
specified from the point of view of the exter-
nal system driving the chip. For example,
t
AVEW
is specified as a minimum since the
external system must supply at least that
much time to meet the worst-case require-
ments of all parts. Responses from the inter-
nal circuitry are specified from the point of
view of the device. Access time, for ex-
ample, is specified as a maximum since
worst-case operation of any device always
provides data within that time.
13. WE is high for the read cycle.
14. The chip is continuously selected (CE
1
low, CE
2
high).
15. All address lines are valid prior-to or
coincident-with the CE
1
and CE
2
transition
to active.
16. The internal write cycle of the memory
is defined by the overlap of CE
1
and CE
2
active and WE low. All three signals must be
active to initiate a write. Any signal can
terminate a write by going inactive. The
address, data, and control input setup and
hold times should be referenced to the sig-
nal that becomes active last or becomes inac-
tive first.
17. If WE goes low before or concurrent
with the latter of CE
1
and CE
2
going active,
the output remains in a high impedance
state.
18. If CE
1
and CE
2
goes inactive before or
concurrent with WE going high, the output
remains in a high impedance state.
19. Powerup from
I
CC2
to
I
CC1
occurs as a
result of any of the following conditions:
a. Rising edge of CE
2
(CE
1
active) or the
falling edge of CE
1
(CE
2
active).
b. Falling edge of WE (CE
1
, CE
2
active).
c. Transition on any address line (CE
1
, CE
2
active).
d. Transition on any data line (CE
1
, CE
2
,
and WE active).
The device automatically powers down
from
I
CC1
to
I
CC2
after
t
PD
has elapsed from
any of the prior conditions. This means that
power dissipation is dependent on only
cycle rate, and is not on Chip Select pulse
width.
INCLUDING
JIG AND
SCOPE
20. At any given temperature and voltage
condition, output disable time is less than
output enable time for any given device.
21. Transition is measured ±200 mV from
steady state voltage with specified loading
in Fig. 1b. This parameter is sampled and
not 100% tested.
22. All address timings are referenced from
the last valid address line to the first transi-
tioning address line.
23. CE
1
, CE
2
, or WE must be inactive during
address transitions.
24. This product is a very high speed device
and care must be taken during testing in
order to realize valid test information. In-
adequate attention to setups and proce-
dures can cause a good part to be rejected as
faulty. Long high inductance leads that
cause supply bounce must be avoided by
bringing the
V
CC
and ground planes di-
rectly up to the contactor fingers. A 0.01 µF
high frequency capacitor is also required
between
V
CC
and ground. To avoid signal
reflections, proper terminations must be
used.
1
2
3
4
5
6
7
F
IGURE
1a.
R
1
480
Ω
+5 V
OUTPUT
8
30 pF
R
2
255
Ω
INCLUDING
JIG AND
SCOPE
9
10
F
IGURE
1b.
+5 V
OUTPUT
R
2
255
Ω
R
1
480
Ω
11
5 pF
F
IGURE
2.
+3.0 V
10%
90%
90%
10%
<3 ns
GND
<3 ns
1M Static RAMs
5-13
03/21/95–LDS.108/9-F
PCB Design
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