S71PL064J08BFI0P4 datasheet, PDF

Datasheet> All Categories > storage> storage> S71PL064J08BFI0P4

S71PL064J08BFI0P4: DescriptionMemory Circuit, Flash+SRAM, CMOS, PBGA56,; Categorystorage storage; File Size4MB，166 Pages; ManufacturerAMD; Websitehttp://www.amd.com; Environmental Compliance

Download Datasheet Parametric View All

S71PL064J08BFI0P4 Overview

Memory Circuit, Flash+SRAM, CMOS, PBGA56,

S71PL064J08BFI0P4 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	AMD
package instruction	FBGA, BGA56,8X8,32
Reach Compliance Code	compli
Maximum access time	65 ns
JESD-30 code	S-PBGA-B56
Memory IC Type	MEMORY CIRCUIT
Mixed memory types	FLASH+SRAM
Number of terminals	56
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	FBGA
Encapsulate equivalent code	BGA56,8X8,32
Package shape	SQUARE
Package form	GRID ARRAY, FINE PITCH
power supply	3/3.3 V
Certification status	Not Qualified
Maximum slew rate	0.07 mA
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM

Preview

Download Datasheet

View All

S71PL254/127/064/032J based

MCPs

Stacked Multi-Chip Product (MCP) Flash Memory and

RAM

128/64/32 Megabit (8/4/2 M x 16-bit) CMOS 3.0 Volt-only

Simultaneous Operation Page Mode Flash Memory and

64/32/16/8/4 Megabit (4M/2M/1M/512K/256K x 16-bit) Static

RAM/Pseudo Static RAM

Distinctive Characteristics

MCP Features

Power supply voltage of 2.7 to 3.1 volt

High performance

— 55 ns

— 65 ns (65 ns Flash, 70ns pSRAM)

Packages

— 7 x 9 x 1.2 mm 56 ball FBGA

— 8 x 11.6 x 1.2 mm 64 ball FBGA

— 8 x 11.6 x 1.4 mm 84 ball FBGA

Operating Temperature

— –25°C to +85°C

— –40°C to +85°C

ADVANCE

General Description

The S71PL series is a product line of stacked Multi-Chip Product (MCP) packages

and consists of:

One or more S29PL (Simultaneous Read/Write) Flash memory die

pSRAM or SRAM

The 256Mb Flash memory consists of two S29PL127J devices. In this case, CE#f2

is used to access the second Flash and no extra address lines are required.

The products covered by this document are listed in the table below:

Flash Memory Density

32Mb

4Mb

8Mb

pSRAM

Density

16Mb

32Mb

64Mb

S71PL032J40

S71PL032J80

S71PL032JA0

S71PL064J80

S71PL064JA0

S71PL064JB0

S71PL127JA0

S71PL127JB0

S71PL127JC0

S71PL254JB0

S71PL254JC0

64Mb

128Mb

256Mb

Flash Memory Density

32Mb

SRAM Density (Note)

Note:

Not Recommended for new designs

64Mb

4Mb

8Mb

S71PL032J04

S71PL032J08

S71PL064J08

Publication Number

S71PL254/127/064/032J_00

Revision

Amendment

Issue Date

May 11, 2004

A d v a n c e

I n f o r m a t i o n

S71PL254/127/064/032J based MCPs

Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1

MCP Features ........................................................................................................ 1

Selecting a Sector Protection Mode ............................................................. 47

Table 12. Sector Protection Schemes ................................... 48

Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 48

Persistent Sector Protection ...........................................................................48

Password Sector Protection ...........................................................................48

WP# Hardware Protection .............................................................................48

Selecting a Sector Protection Mode .............................................................48

General Description . . . . . . . . . . . . . . . . . . . . . . . . 1

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2

32 Mb Flash Memory ............................................................................................2

64 Mb Flash Memory ............................................................................................2

128 Mb Flash Memory ..........................................................................................2

256 Mb Flash Memory (2xS29PL127J) ..............................................................2

Persistent Sector Protection . . . . . . . . . . . . . . . . 49

Persistent Protection Bit (PPB) ......................................................................49

Persistent Protection Bit Lock (PPB Lock) .................................................49

Persistent Sector Protection Mode Locking Bit ........................................ 51

Connection Diagram (S71PL032J)

Connection Diagram (S71PL064J)

Connection Diagram (S71PL127J)

Connection Diagram (S71PL254J)

. . . . . . . . . . . . . .7

. . . . . . . . . . . . . .8

. . . . . . . . . . . . . .9

. . . . . . . . . . . . . 10

Password Protection Mode . . . . . . . . . . . . . . . . . . 51

Password and Password Mode Locking Bit ................................................. 51

64-bit Password .................................................................................................. 52

Write Protect (WP#) ....................................................................................... 52

Persistent Protection Bit Lock ................................................................... 52

High Voltage Sector Protection ..................................................................... 53

Figure 1. In-System Sector Protection/Sector Unprotection

Algorithms........................................................................ 54

Special Handling Instructions For FBGA Package ................................. 10

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 11

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 16

TLC056—56-ball Fine-Pitch Ball Grid Array (FBGA)

9 x 7 mm Package ............................................................................................... 16

TLA064—64-ball Fine-Pitch Ball Grid Array (FBGA)

8 x 11.6 mm Package ............................................................................................17

FTA084—84-ball Fine-Pitch Ball Grid Array (FBGA)

8 x 11.6 mm ............................................................................................................ 18

Temporary Sector Unprotect ........................................................................ 55

Figure 2. Temporary Sector Unprotect Operation ................... 55

S71PLxxxJ/S29PL064J/S29PL032J for MCP

SecSi™ (Secured Silicon) Sector Flash Memory Region .......................... 55

Factory-Locked Area (64 words) .............................................................. 55

Customer-Lockable Area (64 words) ...................................................... 56

SecSi Sector Protection Bits ....................................................................... 56

Figure 3. SecSi Sector Protect Verify .................................... 57

General Description 22

Simultaneous Read/Write Operation with Zero Latency ..................... 22

Page Mode Features .......................................................................................... 22

Standard Flash Memory Features .................................................................. 22

Product Selector Guide . . . . . . . . . . . . . . . . . . . . .24

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Simultaneous Read/Write Block Diagram . . . . . 26

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .28

Table 1. PL127J Device Bus Operations ................................ 28

Hardware Data Protection ............................................................................. 57

Low VCC Write Inhibit ................................................................................ 57

Write Pulse “Glitch” Protection ............................................................... 57

Logical Inhibit ................................................................................................... 57

Power-Up Write Inhibit ............................................................................... 57

Common Flash Memory Interface (CFI) . . . . . . 58

Table 13. CFI Query Identification String .............................. 58

Table 14. System Interface String ........................................ 59

Table 15. Device Geometry Definition ................................... 59

Table 16. Primary Vendor-Specific Extended Query ................ 60

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 62

Reading Array Data ...........................................................................................62

Reset Command .................................................................................................62

Autoselect Command Sequence .................................................................... 63

Enter SecSi™ Sector/Exit SecSi Sector Command Sequence ................ 63

Word Program Command Sequence ........................................................... 63

Unlock Bypass Command Sequence ........................................................64

Figure 4. Program Operation ............................................... 65

Requirements for Reading Array Data ........................................................ 28

Random Read (Non-Page Read) ............................................................... 28

Page Mode Read ............................................................................................. 29

Table 2. Page Select .......................................................... 29

Simultaneous Read/Write Operation .......................................................... 29

Table 3. Bank Select .......................................................... 29

Writing Commands/Command Sequences ................................................ 30

Accelerated Program Operation .............................................................. 30

Autoselect Functions .................................................................................... 30

Automatic Sleep Mode .......................................................................................31

RESET#: Hardware Reset Pin ..........................................................................31

Output Disable Mode .........................................................................................31

Table 4. PL127J Sector Architecture ..................................... 32

Table 5. PL064J Sector Architecture ..................................... 39

Table 6. PL032J Sector Architecture ..................................... 42

Table 7. SecSiTM Sector Addresses ...................................... 43

Chip Erase Command Sequence ................................................................... 65

Sector Erase Command Sequence ................................................................66

Figure 5. Erase Operation ................................................... 67

Erase Suspend/Erase Resume Commands .................................................. 67

Command Definitions Tables .........................................................................68

Table 17. Memory Array Command Definitions ...................... 68

Table 18. Sector Protection Command Definitions .................. 69

Write Operation Status . . . . . . . . . . . . . . . . . . . . 70

DQ7: Data# Polling ............................................................................................70

Figure 6. Data# Polling Algorithm ........................................ 72

Autoselect Mode ................................................................................................ 44

Table 8. Autoselect Codes (High Voltage Method) .................. 44

Table 9. PL127J Boot Sector/Sector Block Addresses for Protection/

Unprotection ..................................................................... 45

Table 10. PL064J Boot Sector/Sector Block Addresses for

Protection/Unprotection ..................................................... 46

Table 11. PL032J Boot Sector/Sector Block Addresses for

Protection/Unprotection ..................................................... 47

DQ6: Toggle Bit I ............................................................................................... 73

Figure 7. Toggle Bit Algorithm ............................................. 74

DQ2: Toggle Bit II .............................................................................................. 74

Reading Toggle Bits DQ6/DQ2 ..................................................................... 74

DQ5: Exceeded Timing Limits ........................................................................ 75

DQ3: Sector Erase Timer ................................................................................ 75

Table 19. Write Operation Status ......................................... 76

May 11, 2004 S71PL254/127/064/032J_00A2

A d v a n c e

I n f o r m a t i o n

Functional Description . . . . . . . . . . . . . . . . . . . .

Absolute Maximum Ratings . . . . . . . . . . . . . . . .

DC Recommended Operating Conditions . . . .

Capacitance (Ta = 25°C, f = 1 MHz) . . . . . . . . .

DC and Operating Characteristics . . . . . . . . . .

128

129

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Functional Description . . . . . . . . . . . . . . . . . . . . . 147

Power Down (for 32M, 64M Only) . . . . . . . . . . . . 147

Power Down .......................................................................................................147

Power Down Program Sequence ................................................................148

Address Key ........................................................................................................148

Common .............................................................................................................. 129

16M pSRAM ......................................................................................................... 130

32M pSRAM ........................................................................................................ 130

64M pSRAM ......................................................................................................... 131

AC Operating Conditions . . . . . . . . . . . . . . . . . . 131

Test Conditions (Test Load and Test Input/Output Reference) ........ 131

Figure 35. Output Load ..................................................... 131

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 133

Read Timings .......................................................................................................133

Figure 36. Timing Waveform of Read Cycle(1)...................... 133

Figure 37. Timing Waveform of Read Cycle(2)...................... 133

Figure 38. Timing Waveform of Read Cycle(2)...................... 133

ACC Characteristics (Ta = -40°C to 85°C, V

= 2.7 to 3.1 V) ........ 132

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 149

Recommended Operating Conditions (See

Warning Below) . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Package Capacitance . . . . . . . . . . . . . . . . . . . . . . 149

DC Characteristics (Under Recommended Condi-

tions Unless Otherwise Noted) . . . . . . . . . . . . . . 150

AC Characteristics (Under Recommended Operat-

ing Conditions Unless Otherwise Noted) . . . . . . .151

Read Operation ..................................................................................................151

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 153

Write Operation ............................................................................................... 153

Write Timings .................................................................................................... 134

Figure 39. Write Cycle #1 (WE# Controlled) ........................ 134

Figure 40. Write Cycle #2 (CS1# Controlled) ....................... 134

Figure 41. Timing Waveform of Write Cycle(3) (CS2 Controlled) ...

135

Figure 42. Timing Waveform of Write Cycle(4) (UB#, LB#

Controlled) ...................................................................... 135

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 154

Power Down Parameters ...............................................................................154

Other Timing Parameters ...............................................................................154

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 155

AC Test Conditions ......................................................................................... 155

AC Measurement Output Load Circuit ..................................................... 155

Figure 51. AC Output Load Circuit...................................... 155

pSRAM Type 6

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Functional Description . . . . . . . . . . . . . . . . . . . . 137

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 137

DC Recommended Operating Conditions (Ta = -

40°C to 85°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

DC Characteristics (Ta = -40°C to 85°C, VDD = 2.6

to 3.3 V) (See Note 3 to 4) . . . . . . . . . . . . . . . . . 137

Capacitance (Ta = 25°C, f = 1 MHz) . . . . . . . . . 138

AC Characteristics and Operating Conditions 138

(Ta = -40°C to 85°C, VDD = 2.6 to 3.3 V) (See Note 5 to 11) ........... 138

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 156

Read Timings .......................................................................................................156

Figure 52. Read Timing #1 (Baisc Timing) .......................... 156

Figure 53. Read Timing #2 (OE# Address Access................. 156

Figure 54. Read Timing #3 (LB#/UB# Byte Access) ............. 157

Figure 55. Read Timing #4 (Page Address Access after CE1#

Control Access for 32M and 64M Only) ............................... 157

Figure 56. Read Timing #5 (Random and Page Address Access for

32M and 64M Only) ......................................................... 158

Write Timings .....................................................................................................158

Figure 57. Write Timing #1 (Basic Timing).......................... 158

Figure 58. Write Timing #2 (WE# Control).......................... 159

Figure 59. Write Timing #3-1 (WE#/LB#/UB# Byte Write Control)

159

Figure 60. Write Timing #3-2 (WE#/LB#/UB# Byte Write Control)

160

Figure 61. Write Timing #3-3 (WE#/LB#/UB# Byte Write Control)

160

Figure 62. Write Timing #3-4 (WE#/LB#/UB# Byte Write Control)

161

AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . 139

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 140

Read Timings ......................................................................................................140

Figure 43. Read Cycle ....................................................... 140

Figure 44. Page Read Cycle (8 Words Access) ...................... 141

Write Timings .................................................................................................... 142

Figure 45. Write Cycle #1 (WE# Controlled) (See Note 8) ..... 142

Figure 46. Write Cycle #2 (CE# Controlled) (See Note 8) ...... 143

Read/Write Timings ...........................................................................................161

Figure 63. Read/Write Timing #1-1 (CE1# Control) ............. 161

Figure 64. Read / Write Timing #1-2 (CE1#/WE#/OE# Control) ...

162

Figure 65. Read / Write Timing #2 (OE#, WE# Control) ....... 162

Figure 66. Read / Write Timing #3 (OE#, WE#, LB#, UB# Control)

163

Figure 67. Power-up Timing #1 ......................................... 163

Figure 68. Power-up Timing #2 ......................................... 164

Figure 69. Power Down Entry and Exit Timing ..................... 164

Figure 70. Standby Entry Timing after Read or Write............ 164

Figure 71. Power Down Program Timing (for 32M/64M Only). 165

Deep Power-down Timing ............................................................................. 143

Figure 47. Deep Power Down Timing................................... 143

Power-on Timing ............................................................................................... 143

Figure 48. Power-on Timing............................................... 143

Provisions of Address Skew ........................................................................... 144

Read .................................................................................................................. 144

Figure 49. Read ............................................................... 144

Write ................................................................................................................ 144

Figure 50. Write ............................................................... 144

pSRAM Type 7

Revision Summary

May 11, 2004 S71PL254/127/064/032J_00A2

Recommended Resources

Second frequency conversion circuit block diagram

One of the air humidity measurement circuits

Radiation field measuring instrument

free oscillating circuit

Computer motherboard circuit diagram 440LX_30

at24c512B I2C write and read: at24c512B uses 16-bit address to store data. So when writing single byte to its eeprom, it is divided into first world address ACK and second world address ACK. So when writing data, should I divide t...; 2592315 51mcu

STM32 serial port printf interrupt sending implementation method: I have a stm32 routine about printf interrupt sending. I didn't understand how the interrupt was triggered when I read the program. The printf sending in the routine requires these two definitions #if...; sinianhuan stm32/stm8

How to hide the desktop in WinCE?: I customized the OS and added my own Shell. Now I found a problem that before my Shell starts, the WinCE desktop will flash. I found that it is because explorer.exe is loaded. If I remove this loading...; friday505 Embedded System

When downloading stm32 using JLink, the error "cannot stop arm device" appears. What is the problem?: Not sure which setting is wrong or if it's something else....; xy03043126 stm32/stm8

c6748 After changing to elf format, the program crashes: The same project, the original configuration is coff, can run normally (simulation), after changing to elf output format, ccs crashes. The direct symptom is that in the following statement, the value ...; Vic DSP and ARM Processors

Classic jokes: An old couple went to take a photo, and the photographer asked: "Uncle, do you want side light, back light, or full light?" The uncle said shyly: "I don't care, can you leave a pair of pants for your ...; phdwong Talking

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components