ATSAMC21E16A-AZTVAO datasheet, PDF

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> ATSAMC21E16A-AZTVAO

ATSAMC21E16A-AZTVAO: DescriptionRISC Microcontroller, 32-Bit, FLASH, 48MHz, CMOS, PQFP32; CategoryThe embedded processor and controller Microcontrollers and processors; File Size9MB，1293 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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ATSAMC21E16A-AZTVAO Overview

RISC Microcontroller, 32-Bit, FLASH, 48MHz, CMOS, PQFP32

ATSAMC21E16A-AZTVAO Parametric

Parameter Name	Attribute value
Maker	Microchip
package instruction	TQFP-32
Reach Compliance Code	compli
ECCN code	3A991.A.2
Has ADC	YES
Address bus width
bit size	32
maximum clock frequency	32 MHz
DAC channel	YES
DMA channel	YES
External data bus width
JESD-30 code	S-PQFP-G32
length	7 mm
Number of I/O lines	26
Number of terminals	32
On-chip program ROM width	8
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	TQFP
Package shape	SQUARE
Package form	FLATPACK, THIN PROFILE
ROM programmability	FLASH
Filter level	AEC-Q100; TS 16949
Maximum seat height	1.2 mm
speed	48 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	2.7 V
Nominal supply voltage	4.5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
width	7 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC

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SAM C20/C21 Family Data

Sheet

32-bit ARM Cortex-M0+ with 5V Support, CAN-FD, PTC,

and Advanced Analog

Features

Operating Conditions

• 2.7V – 5.5V, -40°C to +125°C, DC to 48 MHz

Core

• ARM

Cortex

-M0+ CPU running at up to 48 MHz

– Single-cycle hardware multiplier

– Micro Trace Buffer

– Memory Protection Unit (MPU)

Memories

• 32/64/128/256 KB in-system self-programmable Flash

• 1/2/4/8 KB independent self-programmable Flash for EEPROM emulation

• 4/8/16/32 KB SRAM Main Memory

System

• Power-on Reset (POR) and Brown-out Detection (BOD)

• Internal and external clock options with 48 MHz to 96 MHz Fractional Digital Phase Locked Loop

(FDPLL96M)

• External Interrupt Controller (EIC) (Interrupt pin debouncing is only available in SAM C21N)

• 16 external interrupts

– Hardware debouncing (only on the 100Pin TQFP)

• One non-maskable interrupt

• Two-pin Serial Wire Debug (SWD) programming, test, and debugging interface

Low-Power

• Idle and Standby Sleep modes

• SleepWalking peripherals

Peripherals

• Hardware Divide and Square Root Accelerator (DIVAS)

• 12-channel Direct Memory Access Controller (DMAC)

• 12-channel Event System

• Up to eight 16-bit Timer/Counters (TC), configurable as either (see

Note):

Note:

Maximum and minimum capture is only available in SAM C21N devices.

– One 16-bit TC with compare/capture channels

– One 8-bit TC with compare/capture channels

2019 Microchip Technology Inc.

Datasheet

DS60001479C-page 1

SAM C20/C21 Family Data Sheet

Table of Contents

Features.......................................................................................................................... 1

1. Configuration Summary...........................................................................................14

2. Ordering Information................................................................................................19

3. Block Diagram......................................................................................................... 20

4. Pinout...................................................................................................................... 22

4.1.

4.2.

4.3.

4.4.

SAM C21E / SAM C20E.............................................................................................................22

SAM C21G / SAM C20G............................................................................................................ 23

SAM C21J / SAM C20J.............................................................................................................. 24

SAM C21N / SAM C20N............................................................................................................ 26

5. Signal Descriptions List........................................................................................... 27

6. I/O Multiplexing and Considerations........................................................................29

6.1.

6.2.

Multiplexed Signals.................................................................................................................... 29

Other Functions..........................................................................................................................35

7. Power Supply and Start-Up Considerations............................................................ 38

7.1.

7.2.

7.3.

7.4.

Power Domain Overview............................................................................................................38

Power Supply Considerations.................................................................................................... 39

Power-Up................................................................................................................................... 41

Power-On Reset and Brown-Out Detector................................................................................. 42

8. Product Mapping..................................................................................................... 43

9. Memories.................................................................................................................47

9.1.

9.2.

9.3.

9.4.

9.5.

9.6.

Embedded Memories................................................................................................................. 47

Physical Memory Map................................................................................................................ 47

NVM User Row Mapping............................................................................................................48

NVM Software Calibration Area Mapping...................................................................................49

NVM Temperature Calibration Area Mapping, SAM C21........................................................... 50

Serial Number............................................................................................................................ 50

10. Processor and Architecture..................................................................................... 52

10.1.

10.2.

10.3.

10.4.

Cortex M0+ Processor............................................................................................................... 52

Nested Vector Interrupt Controller..............................................................................................54

Micro Trace Buffer...................................................................................................................... 57

High-Speed Bus System............................................................................................................ 58

11. PAC - Peripheral Access Controller.........................................................................61

11.1. Overview.................................................................................................................................... 61

11.2. Features..................................................................................................................................... 61

2019 Microchip Technology Inc.

Datasheet

DS60001479C-page 4

SAM C20/C21 Family Data Sheet

11.3.

11.4.

11.5.

11.6.

11.7.

Block Diagram............................................................................................................................ 61

Product Dependencies............................................................................................................... 61

Functional Description................................................................................................................63

Register Summary......................................................................................................................66

Register Description................................................................................................................... 67

12. Peripherals Configuration Summary........................................................................87

12.1. SAM C20/C21 N.........................................................................................................................88

12.2. SAM C20/C21 E/G/J.................................................................................................................. 93

13. DSU - Device Service Unit...................................................................................... 97

13.1. Overview.................................................................................................................................... 97

13.2. Features..................................................................................................................................... 97

13.3. Block Diagram............................................................................................................................ 98

13.4. Signal Description...................................................................................................................... 98

13.5. Product Dependencies............................................................................................................... 98

13.6. Debug Operation........................................................................................................................ 99

13.7. Chip Erase................................................................................................................................101

13.8. Programming............................................................................................................................102

13.9. Intellectual Property Protection................................................................................................ 102

13.10. Device Identification................................................................................................................. 104

13.11. Functional Description..............................................................................................................105

13.12. Register Summary....................................................................................................................110

13.13. Register Description................................................................................................................. 112

14. DIVAS – Divide and Square Root Accelerator.......................................................135

14.1.

14.2.

14.3.

14.4.

14.5.

14.6.

14.7.

14.8.

Overview.................................................................................................................................. 135

Features................................................................................................................................... 135

Block Diagram.......................................................................................................................... 135

Signal Description.................................................................................................................... 135

Product Dependencies............................................................................................................. 135

Functional Description..............................................................................................................136

Register Summary....................................................................................................................139

Register Description................................................................................................................. 139

15. Clock System.........................................................................................................147

15.1.

15.2.

15.3.

15.4.

15.5.

15.6.

15.7.

Clock Distribution..................................................................................................................... 147

Synchronous and Asynchronous Clocks..................................................................................148

Register Synchronization......................................................................................................... 148

Enabling a Peripheral............................................................................................................... 150

On-demand, Clock Requests................................................................................................... 150

Power Consumption vs. Speed................................................................................................ 151

Clocks after Reset.................................................................................................................... 151

16. GCLK - Generic Clock Controller.......................................................................... 152

16.1. Overview.................................................................................................................................. 152

16.2. Features................................................................................................................................... 152

16.3. Block Diagram.......................................................................................................................... 152

2019 Microchip Technology Inc.

Datasheet

DS60001479C-page 5

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