MAX24410EXG+ datasheet, PDF - EEWORLD Datasheet

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MAX24410EXG+: DescriptionClock Generator, 750MHz, CMOS, PBGA81; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，59 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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MAX24410EXG+ Overview

Clock Generator, 750MHz, CMOS, PBGA81

MAX24410EXG+ Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Microchip
package instruction	LBGA, BGA81,9X9,40
Reach Compliance Code	compli
JESD-30 code	S-PBGA-B81
length	10 mm
Number of terminals	81
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	750 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA81,9X9,40
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Master clock/crystal nominal frequency	52 MHz
Maximum seat height	1.47 mm
Maximum slew rate	455 mA
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC

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Data Sheet

November 2016

5- or 10-Output Any-to-Any Clock Multipliers

General Description

The MAX24405 and MAX24410 are flexible, high-

performance clock multiplier/synthesizer ICs with two

independent APLLs. Each APLL performs any-to-any

frequency conversion. From any input clock frequency

9.72MHz to 750MHz these devices can produce

frequency-locked APLL output frequencies up to

750MHz and as many as 10 differential output clock

signals that are integer divisors of the APLL

frequencies. Output jitter is typically 0.18 to 0.3ps RMS

for an integer multiply and 0.25 to 0.4ps RMS for a

fractional multiply (12kHz to 20MHz). Each device can

configure itself from an external EEPROM so that clock

signals are available immediately after power-up or

reset.

MAX24405, MAX24410

Features



Input Clocks



One Crystal or CMOS Input

Three Differential or CMOS Inputs

Differential to 750MHz, CMOS to 160MHz

Clock Selection By Pin or Register Control

APLLs Perform High Resolution Fractional-N

Clock Multiplication

Any Output Frequency from <1Hz to 750MHz

Each Output Has an Independent Divider

Output Jitter Typically 0.18 to 0.3ps RMS for

Integer Multiply and 0.25 to 0.4ps RMS for

Fractional Multiply (12kHz to 20MHz)

Outputs are CML or 2xCMOS, Can Interface to

LVDS, LVPECL, HSTL, SSTL and HCSL

CMOS Output Voltage from 1.5V to 3.3V

Automatic Self-Configuration at Power-Up

from External EEPROM Memory

SPI™ Processor Interface

1.8V + 3.3V Operation (5V Tolerant)

-40 to +85

C

Operating Temp. Range



Two APLLs Plus 5 or 10 Output Clocks



Applications

Frequency conversion and synthesis applications in a

wide variety of equipment types



Ordering Information

PART

MAX24405EXG+

MAX24410EXG+

OUTPUTS

TEMP

RANGE

-40 to +85

PIN-

PACKAGE

81-CSBGA



General Features



+Denotes

a lead(Pb)-free/RoHS-compliant package.

18.

Block Diagram

APLL1

3.7-4.2GHz,

Sub-ps jitter,

Fractional-N

DIV1

DIV2

DIV3

DIV4

DIV5

DIV6

DIV7

DIV8

DIV9

DIV10

OC1POS/NEG

OC2POS/NEG

OC3POS/NEG

OC4POS/NEG

OC5POS/NEG

OC6POS/NEG

OC7POS/NEG

OC8POS/NEG

OC9POS/NEG

OC10POS/NEG

Figure 4-2

IC1POS/NEG

IC2POS/NEG

IC3POS/NEG

XIN

XOUT

APLL2

3.7-4.2GHz,

Sub-ps jitter,

Fractional-N

MAX24410 only

Processor SPI Port

EEPROM SPI Port

and HW Control and Status Pins

JTAG

RST_N

TEST

INTREQ

GPIO1

GPIO2

AC / GPIO3

SS / GPIO4

JTRST_N

JTMS

JTCLK

JTDI

JTDO

CS_N

SCLK

SDI

SDO

ECS_N

ESCLK

ESDI

ESDO

MAX24405, MAX24410

Table of Contents

2.1

2.2

2.3

4.1

4.2

4.3

4.4

4.5

APPLICATION EXAMPLES .......................................................................................................... 4

DETAILED FEATURES ................................................................................................................. 5

APLL F

EATURES

.......................................................................................................................... 5

UTPUT

LOCK

EATURES

........................................................................................................... 5

ENERAL

EATURES

.................................................................................................................... 5

PIN DESCRIPTIONS ..................................................................................................................... 6

FUNCTIONAL DESCRIPTION ...................................................................................................... 9

EVICE

DENTIFICATION AND

ROTECTION

..................................................................................... 9

OCAL

SCILLATOR OR

RYSTAL

.................................................................................................. 9

External Oscillator ...................................................................................................................................9

On-Chip Crystal Oscillator ......................................................................................................................9

4.2.1

4.2.2

NPUT

IGNAL

ORMAT

ONFIGURATION

.......................................................................................10

APLL C

ONFIGURATION

................................................................................................................11

Input Selection and Frequency ............................................................................................................ 11

Output Frequency ................................................................................................................................ 11

Enable, Signal Format, Voltage and Interfacing .................................................................................. 12

Frequency Configuration ...................................................................................................................... 13

Phase Adjustment ................................................................................................................................ 13

4.4.1

4.4.2

4.5.1

4.5.2

4.5.3

UTPUT

LOCK

ONFIGURATION

.................................................................................................12

4.6

4.7

4.8

4.9

5.1

ICROPROCESSOR

NTERFACE

....................................................................................................14

ESET

OGIC

..............................................................................................................................16

OWER

-S

UPPLY

ONSIDERATIONS

...............................................................................................16

NITIALIZATION AND

EEPROM C

ONFIGURATION

EMORY

..............................................................16

REGISTER DESCRIPTIONS ........................................................................................................17

EGISTER

YPES

........................................................................................................................17

Status Bits ............................................................................................................................................ 17

Configuration Fields ............................................................................................................................. 17

Bank-Switched Registers ..................................................................................................................... 17

5.1.1

5.1.2

5.1.3

5.2

5.3

EGISTER

...........................................................................................................................18

EGISTER

EFINITIONS

...............................................................................................................19

Global Registers................................................................................................................................... 19

GPIO Registers .................................................................................................................................... 24

APLL Registers .................................................................................................................................... 27

Output Clock Registers ........................................................................................................................ 33

5.3.1

5.3.2

5.3.3

5.3.4

6.1

6.2

6.3

6.4

8.1

8.2

9.1

9.2

JTAG AND BOUNDARY SCAN ...................................................................................................37

JTAG D

ESCRIPTION

....................................................................................................................37

JTAG TAP C

ONTROLLER

TATE

ACHINE

ESCRIPTION

..............................................................38

JTAG I

NSTRUCTION

EGISTER AND

NSTRUCTIONS

.......................................................................40

JTAG T

EST

EGISTERS

...............................................................................................................41

ELECTRICAL CHARACTERISTICS ............................................................................................42

PIN ASSIGNMENTS.....................................................................................................................51

MAX24405 P

SSSIGNMENT

....................................................................................................51

MAX24410 P

SSSIGNMENT

....................................................................................................53

PACKAGE AND THERMAL INFORMATION ...............................................................................55

ACKAGE

ARK

ORMAT

......................................................................................................55

HERMAL

PECIFICATIONS

...........................................................................................................56

MAX24405, MAX24410

10.

11.

ACRONYMS AND ABBREVIATIONS ..........................................................................................57

DATA SHEET REVISION HISTORY ........................................................................................... 58

List of Figures

Figure 1-1. Frequency Synthesis Application Example ................................................................................................4

Figure 1-2. Frequency Conversion Application Example .............................................................................................4

Figure 4-1. Crystal Equivalent Circuit / Crystal and Capacitor Connections ............................................................. 10

Figure 4-2. APLL Block Diagram ............................................................................................................................... 11

Figure 4-3. SPI Read Transaction Functional Timing................................................................................................ 15

Figure 4-4. SPI Write Enable Transaction Functional Timing ................................................................................... 15

Figure 4-5. SPI Write Transaction Functional Timing ................................................................................................ 15

Figure 6-1. JTAG Block Diagram ............................................................................................................................... 37

Figure 6-2. JTAG TAP Controller State Machine ...................................................................................................... 39

Figure 7-1. Recommended External Components for Interfacing to Differential Inputs ............................................ 44

Figure 7-2. Recommended External Components for Interfacing to CML Outputs ................................................... 46

Figure 7-3. Recommended Confguration for Interfacing to HCSL Components ....................................................... 47

Figure 7-4. SPI Interface Timing Diagram ................................................................................................................. 49

Figure 7-5. JTAG Timing Diagram ............................................................................................................................. 50

Figure 8-1. MAX24405 Pin Assignment Diagram ...................................................................................................... 52

Figure 8-2. MAX24410 Pin Assignment Diagram ...................................................................................................... 54

Figure 9-1. Device Top Mark ..................................................................................................................................... 55

List of Tables

Table 3-1. Input Clock Pin Descriptions .......................................................................................................................6

Table 3-2. Output Clock Pin Descriptions .....................................................................................................................6

Table 3-3. Global Pin Descriptions ...............................................................................................................................6

Table 3-4. SPI Interface Pin Descriptions .....................................................................................................................7

Table 3-5. External EEPROM SPI Interface Pin Descriptions ......................................................................................7

Table 3-6. JTAG Interface Pin Descriptions .................................................................................................................7

Table 3-7. Power-Supply Pin Descriptions ...................................................................................................................7

Table 4-1. Crystal Selection Parameters ................................................................................................................... 10

Table 4-2. Input Clock Capabilities ............................................................................................................................ 11

Table 5-1. Register Map ............................................................................................................................................ 18

Table 6-1. JTAG Instruction Codes ........................................................................................................................... 40

Table 6-2. JTAG ID Code .......................................................................................................................................... 41

Table 7-1. Recommended DC Operating Conditions ................................................................................................ 42

Table 7-2. Electrical Characteristics: Supply Currents .............................................................................................. 42

Table 7-3. Electrical Characteristics: Non-Clock CMOS/TTL Pins ............................................................................ 43

Table 7-4. Electrical Characteristics: Clock Inputs .................................................................................................... 44

Table 7-5. Electrical Characteristics: CML Clock Outputs ......................................................................................... 45

Table 7-6. Electrical Characteristics: CMOS and HSTL (Class I) Clock Outputs ...................................................... 46

Table 7-7. Electrical Characteristics: Clock Output Timing ....................................................................................... 47

Table 7-8. Electrical Characteristics: Jitter Specifications ......................................................................................... 47

Table 7-9. Electrical Characteristics: Typical Output Jitter Performance .................................................................. 47

Table 7-10. Electrical Characteristics: Typical Input-to-Output Clock Delay ............................................................. 48

Table 7-11. Electrical Characteristics: Typical Output-to-Output Clock Delay .......................................................... 48

Table 7-12. Electrical Characteristics: SPI Interface Timing ..................................................................................... 49

Table 7-13. Electrical Characteristics: External EEPROM SPI Interface Timing ...................................................... 49

Table 7-14. Electrical Characteristics: JTAG Interface Timing .................................................................................. 50

Table 8-1. MAX24405 Pin Assignments Sorted by Signal Name .............................................................................. 51

Table 8-2. MAX24410 Pin Assignments Sorted by Signal Name .............................................................................. 53

Table 9-1. Package Top Mark Legend ...................................................................................................................... 55

Table 9-2. CSBGA Package Thermal Properties ...................................................................................................... 56

MAX24410EXG+ Related Products

	MAX24410EXG+	MAX24405EXG+	MAX24405EXG2
Description	Clock Generator, 750MHz, CMOS, PBGA81	Clock Generator, 750MHz, CMOS, PBGA81	Processor Specific Clock Generator, 750MHz, CMOS, PBGA81
Is it Rohs certified?	conform to	conform to	conform to
Maker	Microchip	Microchip	Microchip
package instruction	LBGA, BGA81,9X9,40	LBGA, BGA81,9X9,40	LBGA, BGA81,9X9,40
Reach Compliance Code	compli	compli	unknow
JESD-30 code	S-PBGA-B81	S-PBGA-B81	S-PBGA-B81
length	10 mm	10 mm	10 mm
Number of terminals	81	81	81
Maximum operating temperature	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C
Maximum output clock frequency	750 MHz	750 MHz	750 MHz
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LBGA	LBGA	LBGA
Encapsulate equivalent code	BGA81,9X9,40	BGA81,9X9,40	BGA81,9X9,40
Package shape	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
Master clock/crystal nominal frequency	52 MHz	52 MHz	52 MHz
Maximum seat height	1.47 mm	1.47 mm	1.47 mm
Maximum slew rate	455 mA	325 mA	325 mA
Maximum supply voltage	1.89 V	1.89 V	1.89 V
Minimum supply voltage	1.71 V	1.71 V	1.71 V
Nominal supply voltage	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM
width	10 mm	10 mm	10 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC	CLOCK GENERATOR, PROCESSOR SPECIFIC	CLOCK GENERATOR, PROCESSOR SPECIFIC
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	-
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	-

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