Features
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Thermal Sensitive Layer Over a 0.35 µm CMOS Array
Image Zone: 0.4 x 11.6 mm
Image Array: 8 × 232 = 1856 Pixels
Pixel Pitch: 50 × 50 µm = 500 dpi Resolution
On-chip 8-bit Analog to Digital Converter
Serial Peripheral Interface (SPI) - 2 Modes:
– Fast Mode at 16 Mbps Max for Imaging
– Slow Mode at 200 kbps Max for Navigation and Control
Die Size: 1.5 × 15 mm
Operating Voltage: 2.3 to 3.6V
Operating Temperature Range: -40° C to 85° C
Finger Sweeping Speed from 2 to 20 cm/Second
Low Power: 4.5 mA (Image Acquisition), 1.5 mA (Navigation), <10 µA (Sleep Mode)
Hard Protective Coating (>4 Million Sweeps)
High Protection from Electrostatic Discharge
Small Form Factor Packaging
Description
This document describes the specifications of Atmel’s AT77C104B fingerprint sensor
dedicated to PDA, cellular and smartphone applications. Based on FingerChip ther-
mal technology, the AT77C104B is a linear sensor that captures fingerprint images by
sweeping the finger over the sensing area. This product embeds true hardware-based
8-way navigation and click functions.
Applications
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Scrolling, Menu and Item Selection for PDAs, Cellular or Smartphone Applications
Cellular and Smartphones-based Security (Device Protection, Network and ISP
Access, E-commerce)
Personal Digital Agenda (PDA) Access
User Authentication for Private and Confidential Data Access
Portable Fingerprint Acquisition
FingerChip
®
Thermal
Fingerprint
Sweep Sensor,
Hardware
Based,
Navigation and
Click Function,
SPI Interface
AT77C104B
Chip-on-board Package
Sweep your finger
to make life easier
Actual size of sensor
5347B–BIOM–08/04
Table 1.
Pin Description for Chip-on-board Package: AT77C104B-CB08V
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Note:
GNDD
GNDA
VDDD
VDDA
SCK
TESTA
MOSI
TPP
MISO
SCANEN
SSS
IRQ
FSS
RST
FPL
G
G
P
P
I
IO
I
P
O
I
I
O
I
I
I
Name
Type
Description
Not connected
Not connected
Not connected
Not connected
Digital ground supply
Analog ground supply - connect to GNDD
Digital power supply
Analog power supply - connect to V
DD
Serial Port Interface (SPI) clock
Reserved for the analog test, not connected
Master-out slave-in data
Temperature stabilization power
Master-in slave-out data
Reserved for the scan test in factory, must be grounded
Slow SPI slave select (active low
Interrupt line to host (active low). Digital test pin
Fast SPI slave select (active low)
Reset and sleep mode control (active high)
Front plane, must be grounded
The die attach is connected to pin 6 and must be grounded. The FPL pin must also be grounded.
2
AT77C104B
5347B–BIOM–08/04
AT77C104B
Figure 1.
Typical Application
VDDD
VDDD
10 kΩ
IRQ
MISO
MOSI
SCK
SSS
FSS
SCANEN
GND
RST
GNDA
FPL
GND
GNDD
VDDA
10µF
TESTA
TPP
VDDD
10µF
VDDA
10 kΩ
NC
VDDD
The pull-up must be implemented for the master controller. The noise should be lower
than 30 mV peak to peak on VDDA.
Figure 2.
Pin Description
NC
NC
NC
NC
GNDD
GNDA
VDDD
VDDA
SCK
TESTA
MOSI
TPP
MISO
SCANEN
SSS
IRQ
FSS
RST
FPL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
The TESTA pin is only used for testing and debugging. The SCANEN pin is not used in
the final application and must be connected to ground.
Warning : SSS and FSS must never be low at the same time. When both SSS and FSS
equal 0, the chip switches to scan test mode. With the SPI protocol, this
configuration is not possible as only one slave at a time can be selected.
However, this configuration works when debugging the system.
3
5347B–BIOM–08/04
Specifications
Table 2.
Absolute Maximum Ratings
Parameter
Power supply voltage
Front plane
Digital input
Temperature stabilization
power
Storage temperature
Lead temperature
(soldering 10 seconds)
Symbol
VDDD, VDDA
FPL
SSS, FSS,
SCK, MOSI
TPP
Tstg
Tleads
Do not solder
Comments
Value
-0.5 to 4.6V
GND to V
DD
+0.5V
GND to V
DD
+0.5V
GND to V
DD
+0.5V
-50 to +100° C
Forbidden
Note: Stresses beyond those listed
under “Absolute Maximum
Ratings” may cause permanent
damage to the device. These are
stress ratings only and functional
operation of the device at these or
any other conditions beyond those
indicated in the operational
sections of this specification is not
implied. Exposure to absolute
maximum rating conditions for
extended periods may affect device
reliability.
Table 3.
Recommended Conditions of Use
Parameter
Positive supply voltage
Front plane
Digital input voltage
Digital output voltage
Digital load
Operating temperature range
Maximum current on TPP
C
L
T
amb
ITPP
Domestic "D" grade
Use of TPP is optional
0
Symbol
V
DD
FPL
Comments
2.5 ±5%
3.3 ±10%
Must be grounded
Min
2.3
Typ
2.5
3.3
GND
CMOS levels
CMOS levels
20
-40 to +85
-
60
50
Max
3.6
Unit
V
V
V
V
pF
°C
mA
Table 4.
Resistance
Parameter
ESD
On pins HBM (Human Body Model) CMOS I/O
On die surface (zap gun) air discharge
Mechanical Abrasion
Number of cycles without lubricant
Multiply by a factor of 20 for correlation with a real finger
Chemical Resistance
Cleaning agent, acid, grease, alcohol, diluted acetone
4 hours
Internal method
200 000
MIL E 12397B
2 kV
±16 kV
MIL-STD-883 method 3015.7
NF EN 6100-4-2
Min Value
Standard Method
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AT77C104B
5347B–BIOM–08/04
AT77C104B
Table 5.
Explanation of Test Levels
Level
I
II
III
IV
V
VI
D
Description
100% production tested at +25°C
100% production tested at +25°C, and sample tested at specified temperatures (AC testing done on sample)
Sample tested only
Parameter is guaranteed by design and/or characterization testing
Parameter is a typical value only
100% production tested at temperature extremes
100% probe tested on wafer at T
amb
= +25°C
Table 6.
Specifications
Parameter
Resolution
Size
Yield: number of bad pixels
Equivalent resistance on TPP pin
Symbol
Test Level
IV
IV
I
I
23
35
Min
Typ
50
8 × 232
5
47
Max
Unit
Micron
Pixel
Bad pixels
Ohm
Power Consumption and DC Characteristics
The following characteristics are applicable to the operating temperature -40° C
≤
Ta
≤
+85° C.
Typical conditions are: power supply = 3.3V; T
amb
= 25° C; F
SCK
= 12 MHz (1600 slices per second); duty cycle = 50%
C
LOAD
120 pF on digital outputs unless otherwise specified.
Table 7.
Power Requirements
Name
V
DD
I
DD
I
DDNAV
I
DDCLI
I
DDSLP
I
DDSTB
Parameter
Positive supply voltage
Current on V
DD
in acquisition mode
Current on V
DD
in navigation mode
Current on V
DD
in click mode
Current on V
DD
in sleep mode
Current on V
DD
in stand-by mode
Conditions
Test Level
I
I
I
I
I
I
Min
2.3
3
1
0.2
Typ
2.5/3.3
4.5
1.5
0.3
Max
3.6
6
2
0.5
10
Unit-
V
mA
mA
mA
µA
Refer to “Power Management” on page 29
Table 8.
Digital Inputs
Logic Compatibility
Name
I
IL
I
IH
Parameter
Low level input current without pull-
up device
(1)
High level input current without
pull-down device
(1)
Conditions
V
I
= 0V
V
I
= V
DD
Test Level
I
I
CMOS
Min
Typ
Max
1
1
Unit
µA
µA
5
5347B–BIOM–08/04
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