Features
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Compatible with MCS-51™ Products
8K Bytes of Factory Programmable QuickFlash
™
Memory
Fully Static Operation: 0 Hz to 20 MHz
Three-Level Program Memory Lock
256 x 8-Bit Internal RAM
32 Programmable I/O Lines
Three 16-Bit Timer/Counters
Eight Interrupt Sources
Programmable Serial Channel
Low Power Idle and Power Down Modes
Description
The AT80F52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K
bytes of QuickFlash memory. The device is manufactured using Atmel’s high density
nonvolatile memory technology and is compatible with the industry standard 80C51
and 80C52 instruction set and pinout. The on-chip QuickFlash allows custom codes to
be quickly programmed in the factory. By combining a versatile 8-bit CPU with Quick-
Flash on a monolithic chip, the Atmel AT80F52 is a powerful microcomputer which
provides a highly flexible and cost effective solution to many embedded control appli-
cations.
(continued)
8-Bit
Microcontroller
with 8K Bytes
QuickFlash
™
Memory
AT80F52
Pin Configurations
(T2) P1.0
(T2 EX) P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
(WR) P3.6
(RD) P3.7
X TA L 2
X TA L 1
GND
PDIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA
ALE
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)
TQFP
(T2 EX)
(T2)
(AD0)
(AD1)
(AD2)
(AD3)
44 42 40
38
36 34
43 41 39
37
35
P1.5
P1.6
P1.7
RST
P3.0
NC
P3.1
P3.2
P3.3
P3.4
P3.5
P1.4
P1.3
P1.2
P1.1
P1.0
NC
VCC
P0.0
P0.1
P0.2
P0.3
INDEX
CORNER
(RXD)
(TXD)
(INT0)
(INT1)
(T0)
(T1)
1
2
3
4
5
6
7
8
9
10
11
13 15 17 19 21
12 14 16 18 20 22
33
32
31
30
29
28
27
26
25
24
23
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA
NC
ALE
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
PLCC
(T2 EX)
(T2)
(AD0)
(AD1)
(AD2)
(AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA
NC
ALE
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
(WR) P3.6
(RD) P3.7
X TA L 2
X TA L 1
GND
GND
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
(RXD)
(TXD)
(INT0)
(INT1)
(T0)
(T1)
P1.5
P1.6
P1.7
RST
P3.0
NC
P3.1
P3.2
P3.3
P3.4
P3.5
6
4
2
44 42 40
1
5
3
4 3 4 13 9
7
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
1 7 1 9 2 1 2 3 2 5 2 72 9
18 20 22 24 26 28
(WR) P3.6
(RD) P3.7
X TA L 2
X TA L 1
GND
NC
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
P1.4
P1.3
P1.2
P1.1
P1.0
NC
VCC
P0.0
P0.1
P0.2
P0.3
INDEX
CORNER
0980A-A–12/97
3-15
Block Diagram
P0.0 - P0.7
P2.0 - P2.7
V
CC
PORT 0 DRIVERS
GND
PORT 2 DRIVERS
RAM ADDR.
REGISTER
RAM
PORT 0
LATCH
PORT 2
LATCH
QUICK
FLASH
B
REGISTER
ACC
STACK
POINTER
PROGRAM
ADDRESS
REGISTER
TMP2
TMP1
BUFFER
ALU
INTERRUPT, SERIAL PORT,
AND TIMER BLOCKS
PC
INCREMENTER
PSW
PROGRAM
COUNTER
PSEN
ALE
EA
RST
PORT 1
LATCH
PORT 3
LATCH
TIMING
AND
CONTROL
INSTRUCTION
REGISTER
DPTR
OSC
PORT 1 DRIVERS
PORT 3 DRIVERS
P1.0 - P1.7
P3.0 - P3.7
3-16
AT80F52
AT80F52
The AT80F52 provides the following standard features: 8K
bytes of QuickFlash, 256 bytes of RAM, 32 I/O lines, three
16-bit timer/counters, a six-vector two-level interrupt archi-
tecture, a full duplex serial port, on-chip oscillator, and
clock circuitry. In addition, the AT80F52 is designed with
static logic for operation down to zero frequency and sup-
ports two software selectable power saving modes. The
Idle Mode stops the CPU while allowing the RAM,
timer/counters, serial port, and interrupt system to continue
functioning. The Power Down Mode saves the RAM con-
tents but freezes the oscillator, disabling all other chip func-
tions until the next hardware reset.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pullups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source
current (I
IL
) because of the internal pullups.
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @
DPTR). In this application, Port 2 uses strong internal pul-
lups when emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @ RI), Port 2
emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some
control signals during QuickFlash verification.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (I
IL
) because of the pullups.
Port 3 also serves the functions of various special features
of the AT89C51, as shown in the following table.
Port 3 also receives some control signals for QuickFlash
verification.
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Functions
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (timer 0 external input)
T1 (timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
Pin Description
V
CC
Supply voltage.
GND
Ground.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high-
impedance inputs.
Port 0 can also be configured to be the multiplexed low-
order address/data bus during accesses to external pro-
gram and data memory. In this mode, P0 has internal pul-
lups.
Port 0 also outputs the code bytes during program verifica-
tion. External pullups are required during program verifica-
tion.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pullups.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (I
IL
) because of the internal pullups.
In addition, P1.0 and P1.1 can be configured to be the
timer/counter 2 external count input (P1.0/T2) and the
timer/counter 2 trigger input (P1.1/T2EX), respectively, as
shown in the following table.
Port 1 also receives the low-order address bytes during
QuickFlash verification.
Port Pin
P1.0
P1.1
Alternate Functions
T2 (external count input to Timer/Counter 2),
clock-out
T2EX (Timer/Counter 2 capture/reload trigger
and direction control)
RST
Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device.
ALE
Address Latch Enable is an output pulse for latching the
low byte of the address during accesses to external mem-
ory.
In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency and may be used for external tim-
ing or clocking purposes. Note, however, that one ALE
pulse is skipped during each access to external data mem-
ory.
3-17
If desired, ALE operation can be disabled by setting bit 0 of
SFR location 8EH. With the bit set, ALE is active only dur-
ing a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no
effect if the microcontroller is in external execution mode.
PSEN
Program Store Enable is the read strobe to external pro-
gram memory.
When the AT80F52 is executing code from external pro-
gram memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during
each access to external data memory.
EA
External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external pro-
gram memory locations starting at 0000H up to FFFFH.
Table 1.
AT80F52 SFR Map and Reset Values
0F8H
0F0H
0E8H
0E0H
0D8H
0D0H
0C8H
0C0H
0B8H
0B0H
0A8H
0A0H
98H
90H
88H
80H
IP
XX000000
P3
11111111
IE
0X000000
P2
11111111
SCON
00000000
P1
11111111
TCON
00000000
P0
11111111
TMOD
00000000
SP
00000111
TL0
00000000
DPL
00000000
TL1
00000000
DPH
00000000
SBUF
XXXXXXXX
PSW
00000000
T2CON
00000000
T2MOD
XXXXXX00
RCAP2L
00000000
RCAP2H
00000000
ACC
00000000
B
00000000
Note, however, that if lock bit 1 is programmed, EA will be
internally latched on reset.
EA should be strapped to V
CC
for internal program execu-
tions.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
0FFH
0F7H
0EFH
0E7H
0DFH
0D7H
TL2
00000000
TH2
00000000
0CFH
0C7H
0BFH
0B7H
0AFH
0A7H
9FH
97H
TH0
00000000
TH1
00000000
PCON
0XXX0000
8FH
87H
3-18
AT80F52
AT80F52
Special Function Registers
A map of the on-chip memory area called the Special Func-
tion Register (SFR) space is shown in Table 1.
Note that not all of the addresses are occupied, and unoc-
cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indetermi-
nate effect.
User software should not write 1s to these unlisted loca-
tions, since they may be used in future products to invoke
Table 2.
T2CON—Timer/Counter 2 Control Register
T2CON Address = 0C8H
Bit Addressable
Bit
TF2
7
EXF2
6
RCLK
5
TCLK
4
EXEN2
3
TR2
2
C/T2
1
CP/RL2
0
Reset Value = 0000 0000B
new features. In that case, the reset or inactive values of
the new bits will always be 0.
Timer 2 Registers:
Control and status bits are contained in
registers T2CON (shown in Table 2) and T2MOD (shown in
Table 4) for Timer 2. The register pair (RCAP2H, RCAP2L)
are the Capture/Reload registers for Timer 2 in 16-bit cap-
ture mode or 16-bit auto-reload mode.
Interrupt Registers:
The individual interrupt enable bits
are in the IE register. Two priorities can be set for each of
the six interrupt sources in the IP register.
Symbol
TF2
EXF2
Function
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either
RCLK = 1 or TCLK = 1.
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 =
1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2
must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial
port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial
port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX
if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
Start/Stop control for Timer 2. TR2 = 1 starts the timer.
Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge
triggered).
Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2
= 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2
= 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Data Memory
The AT80F52 implements 256 bytes of on-chip RAM. The
upper 128 bytes occupy a parallel address space to the
Special Function Registers. That means the upper 128
bytes have the same addresses as the SFR space but are
physically separate from SFR space.
When an instruction accesses an internal location above
address 7FH, the address mode used in the instruction
specifies whether the CPU accesses the upper 128 bytes
of RAM or the SFR space. Instructions that use direct
addressing access SFR space.
For example, the following direct addressing instruction
accesses the SFR at location 0A0H (which is P2).
MOV 0A0H, #data
Instructions that use indirect addressing access the upper
128 bytes of RAM. For example, the following indirect
addressing instruction, where R0 contains 0A0H, accesses
the data byte at address 0A0H, rather than P2 (whose
address is 0A0H).
MOV @R0, #data
Note that stack operations are examples of indirect
addressing, so the upper 128 bytes of data RAM are avail-
able as stack space.
3-19
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