Features
•
Clock Controller
– 80C51 core with 6 clocks per instruction
– 8 MHz On-Chip Oscillator
– PLL for generating 96 MHz clock to supply CPU core, USB and Smart Card Interfaces
– Programmable CPU clock from 500 kHz / X1 to 48 MHz / X1
Reset Controller
– Power On Reset (POR) feature avoiding an external reset capacitor
– Power Fail Detector (PFD)
– Watch-Dog Timer
Power Management
– Two power saving modes: Idle and Power Down
– Four Power Down Wake-up Sources: Smart Card Detection, Keyboard Interrupt, USB
Resume, External Interrupt
– Input Voltage Range: 4.5V - 5.5V
– Core’s Power Consumption (Without Smart Card and USB):
•30 mA Maximum Operating Current @ 48 MHz / X1
•200
µA
Maximum Power-down Current @ 5.5V
Interrupt Controller
– up to 7 interrupt sources
– up to 4 Level Priority
Memory Controller
– Internal Program memory: up to 16 Kbytes of ROM
– Internal Data Memory : 768 bytes including 256 bytes of data and 512 bytes of XRAM
Two 16-bit Timer/Counters
USB 2.0 Full Speed Interface
– 48 MHz DPLL
– On-Chip 3.3V USB voltage regulator and transceivers
– Software detach feature
– 7 endpoints programmable with In or out directions and ISO, Bulk or Interrupt Transfers :
•Endpoint 0: 32 Bytes Bidirectionnal FIFO for Control transfers
•Endpoints 1,2,3: 8 bytes FIFO
•Endpoints 4,5: 64 Bytes FIFO
•Endpoint 6: 2*64 bytes FIFO with Pin-Pong feature
ISO 7816 UART Interface Fully Compliant with EMV2000, GIE-CB and WHQL Standards
– Programmable ISO clock from 1 MHz to 4.8 MHz
– Card insertion/removal detection with automatic deactivation sequence
– Programmable Baud Rate Generator from 372 to 11.625 clock pulses
– Synchronous/Asynchronous Protocols T=0 and T=1 with Direct or Inverse Convention
– Automatic character repetition on parity errors
– 32 Bit Waiting Time Counter
– 16 Bit Guard Time Counter
– Internal Step Up/Down Converter with Programmable Voltage Output:
•1.8V-30mA, 3V-50mA and 5V-60mA
– Current overload protection
– 6 kV ESD (MIL/STD 833 Class 3) protection on whole Smart Card Interface
Alternate Smart Card Interface with CLK, IO and RST
UART Interface with Integrated Baud Rate Generator (BRG)
Four 12 I/O bit Ports
– Up to four LED outputs with 3 level programmable current source: 2, 4 and 10 mA
– Two General Purpose I/O programmable as external interrupts
Packages
– VQFP32, QFN32, Die
•
•
•
•
•
•
C51
Microcontroller
with USB and
Smart Card
Reader
Interfaces
AT83C5127
Summary
•
•
•
•
•
For detailed functional description,
please refer to the AT8xC5122/23
datasheet.
7519A–SCR–04/05
1
Product description
AT83C5127 product is high-performance CMOS derivatives of the 80C51 8-bit micro-
controllers designed for USB smart card reader applications.
The AT83C5127 is a low pin count of the AT8xC5122 and is proposed in ROM version.
The ROM device is only factory programmable.
Block Diagram
VSS
VCC
INT[0-1]
CRST1
CCLK1
3.3 V
Regulator
X
TAL1
X
TAL2
8 MHz
Oscillator
256 x 8
RAM
80C518-BIT CORE
256 x 8
RAM
512 x 8
X
RAM
UART
Interface
16-BIT
TIMERS
Interrupt
Controller
Alternate
Card
DC/DC
Converter
ISO 7816
Interface
CVSS
T[0-1]
L
I
CVCC
CIO1
RxD
TxD
CP S
RE
CRS
T
CCLK
CIO
CC4
CC8
PLLF
PLL
INTERNALADDRESSANDDATABUS
RS
T
WATCH-DOG
PR
O
P
FD
RESET
16K x 8
RO
M
ParallelI/OPorts
3-BIT
P RT
O
8-BIT
P RT
O
1-BIT
P RT
O
LED's
US
B
Interface
3.3V
Regulator
D+
D-
VREF
2
AT83C5127
7519A–SCR–04/05
P1[2,6-7]
LED[0-3]
P3[0-7]
AVCC
AVSS
DVCC
P5.0
AT83C5127
Package Description
Figure 1.
VQFP32 Package Pinout
CIO
P1.7/CCLK1
D-
AVCC
PLLF
VREF
32 31 30 29 28 27 26 25
DVCC
P1.2/CPRES
CC8
CRST
CC4
CCLK
P5.0
VSS
AVSS
D+
1
2
3
4
5
6
7
8
CVCC
VQFP32
24
23
22
21
20
19
18
17
P3.1/TxD
P1.6
P3.0/RxD
P3.5/T1/CRST1
P3.2/INT0/LED0/CIO1
P3.3/INT1
P3.4/T0/LED1
P3.6/LED2
9 10 11 12 13 14 15 16
LI
CVSS
VREF
P3.7/LED3
XTAL1
XTAL2
RST
D-
AVCC
PLLF
AVSS
VCC
D+
Figure 2.
MLF32 Package Pinout
CIO
P1.7/CCLK1
32 31 30 29 28 27 26 25
DVCC
P1.2/CPRES
CC8
CRST
CC4
CCLK
P5.0
VSS
1
2
3
4
5
6
7
8
CVCC
MLF32
24
23
22
21
20
19
18
17
P3.1/TxD
P1.6
P3.0/RxD
P3.5/T1/CRST1
P3.2/INT0/LED0/CIO1
P3.3/INT1
P3.4/T0/LED1
P3.6/LED2
9 10 11 12 13 14 15 16
P3.7/LED3
XTAL1
XTAL2
RST
LI
CVSS
VCC
3
7519A–SCR–04/05
Pin Description
Table 1.
Pin Description
LQFP32
QFN32
Internal
Power
Supply
CVCC
ESD
6KV
I/O
I/O
Reset
Level
0
Alt
CIO
Reset
Config
Port51
Conf 1
Conf 2
Conf 3
Led
Port
CIO
32
32
CVCC inactive at reset.
ESD tested with a 10µF on CVCC
CVCC inactive at reset
ESD tested with a 10µF on CVCC
Weak & medium pull-up can be
disconnected
CVCC inactive at reset
ESD tested with a 10µF on CVCC
CVCC inactive at reset
ESD tested with a 10µF on CVCC
CVCC inactive at reset
ESD tested with a 10µF on CVCC
CC4
3
3
CVCC
6KV
I/O
0
CC8
Port51
P1.2
2
2
VCC
2KV
I/O
1
CPRES
Port51
CC4
5
5
CVCC
6KV
I/O
0
CC4
Port51
CCLK
6
6
CVCC
6KV
O
0
CCLK
Push-pull
CRST
4
4
CVCC
6KV
O
0
CRST
Push-pull
P1.6
P1.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P5.0
23
31
22
24
20
19
18
21
17
13
7
23
31
22
24
20
19
18
21
17
13
7
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
2KV
2KV
2KV
2KV
2KV
2KV
2KV
2KV
2KV
2KV
2KV
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
1
1
1
1
1
1
1
1
1
1
Reset Input
CCLK1
RxD
TxD
INT0
INT1
T0
T1
Port51
Port51
Port51
Port51
Port51
Port51
Port51
Port51
Port51
Port51
Port51
Push-pull
LED2
LED3
Push-pull
Push-pull
LED1
Push-pull
Push-pull
LED0
The Port pins are driven to their reset conditions when a voltage lower
than V
IL
is applied, whether or not the oscillator is running.
RST
16
16
VCC
I/0
This pin has an internal 10K pull-up resistor which allows the device to
be reset by connecting a capacitor between this pin and VSS.
Asserting RST when the chip is in Idle mode or Power-Down mode
returns the chip to normal operation.
The output is active for at least 12 oscillator periods when an internal
reset occurs.
4
AT83C5127
7519A–SCR–04/05
AT83C5127
Table 1.
Pin Description (Continued)
LQFP32
QFN32
Internal
Power
Supply
ESD
I/O
Reset
Level
Alt
Reset
Config
Conf 1
Conf 2
Conf 3
Led
Port
USB Positive Data Upstream Port
D+
29
29
DVCC
I/O
This pin requires an external serial resistor of 33Ω and a 1.5 K
Ω
pull-
up to
V
REF for full speed configuration.
USB Negative Data Upstream Port
This pin requires an external serial resistor of 33Ω
USB Voltage Reference:
3.0 <
V
REF < 3.6 V
D-
28
28
DVCC
I/O
V
REF
30
30
AVCC
O
V
REF
can be connected to D+ through a 1.5 K
Ω
resistor. The
V
REF
voltage is controlled by software.
Input to the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal or an external oscillator must be
connected to this pin.
Output of the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal circuit must be connected to
this pin. If an external oscillator is used, leave XTAL2 unconnected.
PLL Low Pass Filter input
Receives the RC network of the PLL low pass filter.
Analog Supply Voltage
XTAL1
14
14
VCC
I
XTAL2
15
15
VCC
O
PLLF
26
26
AVCC
O
AVCC
27
27
PWR
AVCC is used to supply the internal 3.3V analog regulator which
supplies the internal USB driver
Supply Voltage
VCC
12
12
PWR
VCC is used to supply the internal 3.3V digital regulator which
supplies the PLL, CPU core and internal I/O’s
DC/DC Input
LI supplies the current for the charge pump of the DC/DC converter.
LI
10
10
PWR
- LI tied directly to VCC : the DC/DC converter must be configured in
regulator mode.
- LI tied to VCC through an external 10µH coil : the DC/DC converter
can be configured either in regulator or in pump mode.
Card Supply Voltage
CVCC
9
9
PWR
CVCC is the ouput of internal DC/DC converter which supplies the
Smart Card Interface. It must be connected to an external decoupling
capacitor of 10 µF with the lowest ESR as this parameter influences
on the CVCC noise
Digital Supply Voltage
DVCC
1
1
PWR
DVCC is the output of the internal analog 3.3V regulator which
supplies the USB driver. This pin must be connected to an external
680nF decoupling capacitor if the USB interface is used.
DC/DC Ground
CVSS is used to sink high shunt currents from the external coil
Digital Ground
VSS is used to supply the PLL, buffer ring and the digital core
Analog Ground
AVSS is used to supply the USB driver.
CVSS
11
11
GND
VSS
AVSS
8
25
8
25
GND
GND
5
7519A–SCR–04/05
京公网安备 11010802033920号
EEWORLD
