Preliminary
‡
1Gb: x16, x32 Mobile LPDDR SDRAM
Features
Mobile Low-Power DDR SDRAM
MT46H64M16LF – 16 Meg x 16 x 4 banks
MT46H32M32LF – 8 Meg x 32 x 4 banks
MT46H32M32LG – 8 Meg x 32 x 4 banks
Features
• V
DD
/V
DDQ
= 1.70–1.95V
• Bidirectional data strobe per byte of data (DQS)
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• 4 internal banks for concurrent operation
• Data masks (DM) for masking write data; one mask
per byte
• Programmable burst lengths (BL): 2, 4, 8, or 16
• Concurrent auto precharge option is supported
• Auto refresh and self refresh modes
• 1.8V LVCMOS-compatible inputs
• Temperature-compensated self refresh (TCSR)
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• Status read register (SRR)
• Selectable output drive strength (DS)
• Clock stop capability
• 64ms refresh, 32ms for automotive temperature
Table 1: Key Timing Parameters (CL = 3)
Speed Grade
-5
-54
-6
-75
Clock Rate
200 MHz
185 MHz
166 MHz
133 MHz
Access Time
5.0ns
5.0ns
5.0ns
6.0ns
Options
• V
DD
/V
DDQ
– 1.8V/1.8V
• Configuration
– 64 Meg x 16 (16 Meg x 16 x 4
banks)
– 32 Meg x 32 (8 Meg x 32 x 4 banks)
• Addressing
– JEDEC-standard
– JEDEC reduced page size
• Plastic "green" package
– 60-ball VFBGA (8mm x 9mm)
1
– 90-ball VFBGA (8mm x 13mm)
2
• PoP (plastic "green" package)
– 152-ball WFBGA (14mm x 14mm)
2
– 168-ball WFBGA (12mm x 12mm)
2
• Timing – cycle time
– 5ns @ CL = 3 (200 MHz)
– 5.4ns @ CL = 3 (185 MHz)
– 6ns @ CL = 3 (166 MHz)
– 7.5ns @ CL = 3 (133 MHz)
• Power
– Standard I
DD2
/I
DD6
• Operating temperature range
– Commercial (0˚ to +70˚C)
– Industrial (–40˚C to +85˚C)
– Industrial/burn-in
3
– Automotive (–40˚C to +105˚C)
4
– Automotive/burn-in
3
• Design revision
Notes:
1.
2.
3.
4.
Marking
H
64M16
32M32
LF
LG
BF
B5
MB
MA
-5
-54
-6
-75
None
None
IT
AIT
AT
AAT
:B
Only available for x16 configuration.
Only available for x32 configuration.
Package-level burn-in.
Contact factory for availability.
PDF: 09005aef84812cd1
1gb_ddr_mobile_sdram_t68m.pdf - Rev. B 3/12 EN
1
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
Preliminary
1Gb: x16, x32 Mobile LPDDR SDRAM
Features
Table 2: Configuration Addressing
Architecture
Configuration
Refresh count
Row addressing
Column addressing
64 Meg x 16
16 Meg x 16 x 4 banks
8K
16K A[13:0]
1K A[9:0]
32 Meg x 32
8 Meg x 32 x 4 banks
8K
8K A[12:0]
1K A[9:0]
Reduced Page Size
32 Meg x 32
8 Meg x 32 x 4 banks
8K
16K A[13:0]
512 A[8:0]
Figure 1: 1Gb Mobile LPDDR Part Numbering
MT 46
Micron Technology
Product Family
46 = Mobile LPDDR
H
64M16 LF BF
-6
AIT :B
Design Revision
:B = Second generation
Operating Temperature
Blank = Commercial (0°C to +70°C)
IT = Industrial (–40°C to +85°C)
AIT = Industrial/burn-in
AT = Automotive (–40°C to +105°C)
AAT = Automotive/burn-in
Operating Voltage
H = 1.8/1.8V
Configuration
64 Meg x 16
32 Meg x 32
Power
Blank = Standard I
DD2
/I
DD6
Addressing
LF = JEDEC-standard
LG = JEDEC reduced page size
Cycle Time (CL = 3)
-5 = 5ns
t
CK
-54 = 5.4ns
t
CK
-6 = 6ns
t
CK
-75 = 7.5ns
t
CK
Package Codes
BF = 60-ball (8mm x 9mm) VFBGA, “green”
B5 = 90-ball (8mm x 13mm) VFBGA, “green”
MB = 152-ball (14mm x 14mm) WFBGA, “green”
MA = 168-ball (12mm x 12mm) WFBGA, “green”
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s FBGA part marking decoder is available at
www.micron.com/decoder.
PDF: 09005aef84812cd1
1gb_ddr_mobile_sdram_t68m.pdf - Rev. B 3/12 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
Preliminary
1Gb: x16, x32 Mobile LPDDR SDRAM
Features
Contents
General Description ......................................................................................................................................... 7
Functional Block Diagrams ............................................................................................................................... 8
Ball Assignments and Descriptions ................................................................................................................. 10
Package Dimensions ....................................................................................................................................... 15
Electrical Specifications .................................................................................................................................. 18
Electrical Specifications – I
DD
Parameters ........................................................................................................ 22
Electrical Specifications – AC Operating Conditions ......................................................................................... 28
Output Drive Characteristics ........................................................................................................................... 33
Functional Description ................................................................................................................................... 36
Commands .................................................................................................................................................... 37
DESELECT ................................................................................................................................................. 38
NO OPERATION ......................................................................................................................................... 38
LOAD MODE REGISTER ............................................................................................................................. 38
ACTIVE ...................................................................................................................................................... 38
READ ......................................................................................................................................................... 39
WRITE ....................................................................................................................................................... 40
PRECHARGE .............................................................................................................................................. 41
BURST TERMINATE ................................................................................................................................... 42
AUTO REFRESH ......................................................................................................................................... 42
SELF REFRESH ........................................................................................................................................... 43
DEEP POWER-DOWN ................................................................................................................................. 43
Truth Tables ................................................................................................................................................... 44
State Diagram ................................................................................................................................................ 49
Initialization .................................................................................................................................................. 50
Standard Mode Register .................................................................................................................................. 53
Burst Length .............................................................................................................................................. 54
Burst Type .................................................................................................................................................. 54
CAS Latency ............................................................................................................................................... 55
Operating Mode ......................................................................................................................................... 56
Extended Mode Register ................................................................................................................................. 57
Temperature-Compensated Self Refresh ...................................................................................................... 57
Partial-Array Self Refresh ............................................................................................................................ 58
Output Drive Strength ................................................................................................................................ 58
Status Read Register ....................................................................................................................................... 59
Bank/Row Activation ...................................................................................................................................... 61
READ Operation ............................................................................................................................................. 62
WRITE Operation ........................................................................................................................................... 73
PRECHARGE Operation .................................................................................................................................. 85
Auto Precharge ............................................................................................................................................... 85
Concurrent Auto Precharge ......................................................................................................................... 86
AUTO REFRESH Operation ............................................................................................................................. 91
SELF REFRESH Operation ............................................................................................................................... 92
Power-Down .................................................................................................................................................. 93
Deep Power-Down ..................................................................................................................................... 95
Clock Change Frequency ................................................................................................................................ 97
Revision History ............................................................................................................................................. 98
Rev. B – 3/12 ............................................................................................................................................... 98
Rev. A – 8/11 ............................................................................................................................................... 98
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1gb_ddr_mobile_sdram_t68m.pdf - Rev. B 3/12 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
Preliminary
1Gb: x16, x32 Mobile LPDDR SDRAM
Features
List of Figures
Figure 1: 1Gb Mobile LPDDR Part Numbering .................................................................................................. 2
Figure 2: Functional Block Diagram (x16) ......................................................................................................... 8
Figure 3: Functional Block Diagram (x32) ......................................................................................................... 9
Figure 4: 60-Ball VFBGA – Top View, x16 only .................................................................................................. 10
Figure 5: 90-Ball VFBGA – Top View, x32 only .................................................................................................. 11
Figure 6: 168-Ball FBGA – 12mm x 12mm (Top View), x32 only ........................................................................ 12
Figure 7: 60-Ball VFBGA (8mm x 9mm), Package Code: BF .............................................................................. 15
Figure 8: 90-Ball VFBGA (8mm x 13mm), Package Code: B5 ............................................................................. 16
Figure 9: 168-Ball WFBGA (12mm x 12mm), Package Code: MA ....................................................................... 17
Figure 10: Typical Self Refresh Current vs. Temperature .................................................................................. 27
Figure 11: ACTIVE Command ........................................................................................................................ 39
Figure 12: READ Command ........................................................................................................................... 40
Figure 13: WRITE Command ......................................................................................................................... 41
Figure 14: PRECHARGE Command ................................................................................................................ 42
Figure 15: DEEP POWER-DOWN Command ................................................................................................... 43
Figure 16: Simplified State Diagram ............................................................................................................... 49
Figure 17: Initialize and Load Mode Registers ................................................................................................. 51
Figure 18: Alternate Initialization with CKE LOW ............................................................................................ 52
Figure 19: Standard Mode Register Definition ................................................................................................. 53
Figure 20: CAS Latency .................................................................................................................................. 56
Figure 21: Extended Mode Register ................................................................................................................ 57
Figure 22: Status Read Register Timing ........................................................................................................... 59
Figure 23: Status Register Definition .............................................................................................................. 60
Figure 24: READ Burst ................................................................................................................................... 63
Figure 25: Consecutive READ Bursts .............................................................................................................. 64
Figure 26: Nonconsecutive READ Bursts ........................................................................................................ 65
Figure 27: Random Read Accesses .................................................................................................................. 66
Figure 28: Terminating a READ Burst ............................................................................................................. 67
Figure 29: READ-to-WRITE ............................................................................................................................ 68
Figure 30: READ-to-PRECHARGE .................................................................................................................. 69
Figure 31: Data Output Timing –
t
DQSQ,
t
QH, and Data Valid Window (x16) .................................................... 70
Figure 32: Data Output Timing –
t
DQSQ,
t
QH, and Data Valid Window (x32) .................................................... 71
Figure 33: Data Output Timing –
t
AC and
t
DQSCK .......................................................................................... 72
Figure 34: Data Input Timing ......................................................................................................................... 74
Figure 35: Write – DM Operation .................................................................................................................... 75
Figure 36: WRITE Burst ................................................................................................................................. 76
Figure 37: Consecutive WRITE-to-WRITE ....................................................................................................... 77
Figure 38: Nonconsecutive WRITE-to-WRITE ................................................................................................. 77
Figure 39: Random WRITE Cycles .................................................................................................................. 78
Figure 40: WRITE-to-READ – Uninterrupting ................................................................................................. 79
Figure 41: WRITE-to-READ – Interrupting ...................................................................................................... 80
Figure 42: WRITE-to-READ – Odd Number of Data, Interrupting ..................................................................... 81
Figure 43: WRITE-to-PRECHARGE – Uninterrupting ....................................................................................... 82
Figure 44: WRITE-to-PRECHARGE – Interrupting ........................................................................................... 83
Figure 45: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting .......................................................... 84
Figure 46: Bank Read – With Auto Precharge ................................................................................................... 87
Figure 47: Bank Read – Without Auto Precharge .............................................................................................. 88
Figure 48: Bank Write – With Auto Precharge .................................................................................................. 89
Figure 49: Bank Write – Without Auto Precharge ............................................................................................. 90
Figure 50: Auto Refresh Mode ........................................................................................................................ 91
PDF: 09005aef84812cd1
1gb_ddr_mobile_sdram_t68m.pdf - Rev. B 3/12 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
Preliminary
1Gb: x16, x32 Mobile LPDDR SDRAM
Features
Figure 51:
Figure 52:
Figure 53:
Figure 54:
Figure 55:
Self Refresh Mode ..........................................................................................................................
Power-Down Entry (in Active or Precharge Mode) ...........................................................................
Power-Down Mode (Active or Precharge) ........................................................................................
Deep Power-Down Mode ...............................................................................................................
Clock Stop Mode ...........................................................................................................................
93
94
95
96
97
PDF: 09005aef84812cd1
1gb_ddr_mobile_sdram_t68m.pdf - Rev. B 3/12 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
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