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MT47H128M8SH-25EAIT:M

Description
DDR DRAM, 128MX8, 0.4ns, CMOS, PBGA60, 8 X 10 MM, ROHS COMPLIANT, FBGA-60
Categorystorage    storage   
File Size9MB,127 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Environmental Compliance
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MT47H128M8SH-25EAIT:M Overview

DDR DRAM, 128MX8, 0.4ns, CMOS, PBGA60, 8 X 10 MM, ROHS COMPLIANT, FBGA-60

MT47H128M8SH-25EAIT:M Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerMicron Technology
package instructionTFBGA,
Reach Compliance Codecompli
access modeMULTI BANK PAGE BURST
Maximum access time0.4 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-PBGA-B60
length10 mm
memory density1073741824 bi
Memory IC TypeDDR DRAM
memory width8
Number of functions1
Number of ports1
Number of terminals60
word count134217728 words
character code128000000
Operating modeSYNCHRONOUS
organize128MX8
Package body materialPLASTIC/EPOXY
encapsulated codeTFBGA
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Filter levelAEC-Q100
Maximum seat height1.2 mm
self refreshYES
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width8 mm

MT47H128M8SH-25EAIT:M Preview

1Gb: x8, x16 Automotive DDR2 SDRAM
Features
Automotive DDR2 SDRAM
MT47H128M8 – 16 Meg x 8 x 8 banks
MT47H64M16 – 8 Meg x 16 x 8 banks
Features
V
DD
= 1.8V ±0.1V, V
DDQ
= 1.8V ±0.1V
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4n-bit prefetch architecture
Duplicate output strobe (RDQS) option for x8
DLL to align DQ and DQS transitions with CK
8 internal banks for concurrent operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency - 1
t
CK
Selectable burst lengths (BL): 4 or 8
Adjustable data-output drive strength
64ms, 8192-cycle refresh
On-die termination (ODT)
RoHS-compliant
Supports JEDEC clock jitter specification
AEC-Q100
PPAP submission
8D response time
Options
1
• Configuration
– 128 Meg x 8 (16 Meg x 8 x 8 banks)
– 64 Meg x 16 (8 Meg x 16 x 8 banks)
• FBGA package (Pb-free) – x16
– 84-ball FBGA (8mm x 12.5mm) Die
Rev :M
• FBGA package (Pb-free) – x8
– 60-ball FBGA (8mm x 10mm) Die
Rev :M
• Timing – cycle time
– 2.5ns @ CL = 5 (DDR2-800)
– 2.5ns @ CL = 6 (DDR2-800)
– 3.0ns @ CL = 5 (DDR2-667)
• Special option
– Standard
– Automotive grade
• Operating temperature
– Industrial (–40°C
T
C
+95°C)
– Automotive (–40°C
T
C
+105°C)
• Revision
Note:
Marking
128M8
64M16
NF
SH
-25E
-25
-3
None
A
IT
AT
:M
1. Not all options listed can be combined to
define an offered product. Use the Part
Catalog Search on www.micron.com for
product offerings and availability.
Table 1: Key Timing Parameters
Data Rate (MT/s)
Speed Grade
-25E
-25E
-3
CL = 3
400
400
400
CL = 4
533
533
533
CL = 5
800
667
667
CL = 6
800
800
n/a
CL = 7
n/a
n/a
n/a
t
RC
(ns)
55
55
55
Table 2: Addressing
Parameter
Configuration
Refresh count
Row address
128 Meg x 8
16 Meg x 8 x 8 banks
8K
A[13:0] (16K)
64 Meg x 16
8 Meg x 16 x 8 banks
8K
A[12:0] (8K)
PDF: 09005aef85a711f4
1gb_ddr2_ait-aat_u88b.pdf – Rev. A 05/14 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
1Gb: x8, x16 Automotive DDR2 SDRAM
Features
Table 2: Addressing (Continued)
Parameter
Bank address
Column address
128 Meg x 8
BA[2:0] (8)
A[9:0] (1K)
64 Meg x 16
BA[2:0] (8)
A[9:0] (1K)
Figure 1: 1Gb DDR2 Part Numbers
MT
Micron Technology
Product Family
47 = DDR2 SDRAM
47
H
32M16
NF
-25E
IT
:H
Design Revision
:H/:M revision
Operating Temperature
IT = Industrial temperature
AT = Automotive temperature
Special Options
Blank = No special options
A = Automotive grade
Operating Voltage
H = 1.8V V
DD
CMOS
Configuration
128M8 = 128 Meg x 8
64M16 = 64 Meg x 16
Cycle Time
-3 =
t
CK = 3.0ns, CL = 5
-25 =
t
CK = 2.5ns, CL = 6
-25E =
t
CK = 2.5ns, CL = 5
Package Codes
HR = 84-ball FBGA, 8mm x 12.5mm
NF = 60-ball FBGA, 8mm x 10mm
SH = 60-ball FBGA, 8mm x 10mm
Note:
1. Not all speeds and configurations are available in all packages.
FBGA Part Number System
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:
http://www.micron.com.
PDF: 09005aef85a711f4
1gb_ddr2_ait-aat_u88b.pdf – Rev. A 05/14 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
1Gb: x8, x16 Automotive DDR2 SDRAM
Features
Contents
State Diagram .................................................................................................................................................. 8
Functional Description ..................................................................................................................................... 9
Automotive Industrial Temperature ............................................................................................................... 9
Automotive Temperature ............................................................................................................................ 10
General Notes ............................................................................................................................................ 10
Functional Block Diagrams ............................................................................................................................. 11
Ball Assignments and Descriptions ................................................................................................................. 13
Packaging ...................................................................................................................................................... 17
Package Dimensions ................................................................................................................................... 17
FBGA Package Capacitance ......................................................................................................................... 19
Electrical Specifications – Absolute Ratings ..................................................................................................... 20
Temperature and Thermal Impedance ........................................................................................................ 20
Electrical Specifications – I
DD
Parameters ........................................................................................................ 22
I
DD
Specifications and Conditions ............................................................................................................... 22
I
DD7
Conditions .......................................................................................................................................... 22
AC Timing Operating Specifications .............................................................................................................. 0
AC and DC Operating Conditions .................................................................................................................... 33
ODT DC Electrical Characteristics ................................................................................................................... 33
Input Electrical Characteristics and Operating Conditions ............................................................................... 34
Output Electrical Characteristics and Operating Conditions ............................................................................. 37
Output Driver Characteristics ......................................................................................................................... 39
Power and Ground Clamp Characteristics ....................................................................................................... 43
AC Overshoot/Undershoot Specification ......................................................................................................... 44
Input Slew Rate Derating ................................................................................................................................ 46
Commands .................................................................................................................................................... 60
Truth Tables ............................................................................................................................................... 60
DESELECT ................................................................................................................................................. 64
NO OPERATION (NOP) ............................................................................................................................... 65
LOAD MODE (LM) ...................................................................................................................................... 65
ACTIVATE .................................................................................................................................................. 65
READ ......................................................................................................................................................... 65
WRITE ....................................................................................................................................................... 65
PRECHARGE .............................................................................................................................................. 66
REFRESH ................................................................................................................................................... 66
SELF REFRESH ........................................................................................................................................... 66
Mode Register (MR) ........................................................................................................................................ 67
Burst Length .............................................................................................................................................. 67
Burst Type .................................................................................................................................................. 69
Operating Mode ......................................................................................................................................... 69
DLL RESET ................................................................................................................................................. 69
Write Recovery ........................................................................................................................................... 69
Power-Down Mode ..................................................................................................................................... 70
CAS Latency (CL) ........................................................................................................................................ 70
Extended Mode Register (EMR) ....................................................................................................................... 72
DLL Enable/Disable ................................................................................................................................... 73
Output Drive Strength ................................................................................................................................ 73
DQS# Enable/Disable ................................................................................................................................. 73
RDQS Enable/Disable ................................................................................................................................. 73
Output Enable/Disable ............................................................................................................................... 73
On-Die Termination (ODT) ......................................................................................................................... 74
PDF: 09005aef85a711f4
1gb_ddr2_ait-aat_u88b.pdf – Rev. A 05/14 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
1Gb: x8, x16 Automotive DDR2 SDRAM
Features
Off-Chip Driver (OCD) Impedance Calibration ............................................................................................ 74
Posted CAS Additive Latency (AL) ................................................................................................................ 74
Extended Mode Register 2 (EMR2) ................................................................................................................... 76
Extended Mode Register 3 (EMR3) ................................................................................................................... 77
Initialization .................................................................................................................................................. 78
ACTIVATE ...................................................................................................................................................... 81
READ ............................................................................................................................................................. 83
READ with Precharge .................................................................................................................................. 87
READ with Auto Precharge .......................................................................................................................... 89
WRITE ........................................................................................................................................................... 95
PRECHARGE ................................................................................................................................................. 106
REFRESH ...................................................................................................................................................... 107
SELF REFRESH .............................................................................................................................................. 108
Power-Down Mode ........................................................................................................................................ 110
Precharge Power-Down Clock Frequency Change ........................................................................................... 117
Reset ............................................................................................................................................................. 118
CKE Low Anytime ...................................................................................................................................... 118
ODT Timing .................................................................................................................................................. 120
MRS Command to ODT Update Delay ........................................................................................................ 122
PDF: 09005aef85a711f4
1gb_ddr2_ait-aat_u88b.pdf – Rev. A 05/14 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
1Gb: x8, x16 Automotive DDR2 SDRAM
Features
List of Figures
Figure 1: 1Gb DDR2 Part Numbers ................................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................... 8
Figure 3: 128 Meg x 8 Functional Block Diagram ............................................................................................. 11
Figure 4: 64 Meg x 16 Functional Block Diagram ............................................................................................. 12
Figure 5: 60-Ball FBGA – x8 Ball Assignments (Top View) ................................................................................ 13
Figure 6: 84-Ball FBGA – x16 Ball Assignments (Top View) ............................................................................... 14
Figure 7: 84-Ball FBGA Package (8mm x 12.5mm) – x16; "NF" Die Rev :M ......................................................... 17
Figure 8: 60-Ball FBGA (8mm x 10mm) – x8; "SH" Die Rev :M .......................................................................... 18
Figure 9: Example Temperature Test Point Location ........................................................................................ 21
Figure 10: Single-Ended Input Signal Levels ................................................................................................... 34
Figure 11: Differential Input Signal Levels ...................................................................................................... 35
Figure 12: Differential Output Signal Levels .................................................................................................... 37
Figure 13: Output Slew Rate Load .................................................................................................................. 38
Figure 14: Full Strength Pull-Down Characteristics ......................................................................................... 39
Figure 15: Full Strength Pull-Up Characteristics .............................................................................................. 40
Figure 16: Reduced Strength Pull-Down Characteristics .................................................................................. 41
Figure 17: Reduced Strength Pull-Up Characteristics ...................................................................................... 42
Figure 18: Input Clamp Characteristics .......................................................................................................... 43
Figure 19: Overshoot ..................................................................................................................................... 44
Figure 20: Undershoot ................................................................................................................................... 44
Figure 21: Nominal Slew Rate for
t
IS ............................................................................................................... 49
Figure 22: Tangent Line for
t
IS ........................................................................................................................ 49
Figure 23: Nominal Slew Rate for
t
IH .............................................................................................................. 50
Figure 24: Tangent Line for
t
IH ....................................................................................................................... 50
Figure 25: Nominal Slew Rate for
t
DS ............................................................................................................. 56
Figure 26: Tangent Line for
t
DS ...................................................................................................................... 56
Figure 27: Nominal Slew Rate for
t
DH ............................................................................................................. 57
Figure 28: Tangent Line for
t
DH ..................................................................................................................... 57
Figure 29: AC Input Test Signal Waveform Command/Address Balls ................................................................ 58
Figure 30: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) ............................................ 58
Figure 31: AC Input Test Signal Waveform for Data with DQS (Single-Ended) ................................................... 59
Figure 32: AC Input Test Signal Waveform (Differential) .................................................................................. 59
Figure 33: MR Definition ............................................................................................................................... 68
Figure 34: CL ................................................................................................................................................. 71
Figure 35: EMR Definition ............................................................................................................................. 72
Figure 36: READ Latency ............................................................................................................................... 75
Figure 37: WRITE Latency .............................................................................................................................. 75
Figure 38: EMR2 Definition ........................................................................................................................... 76
Figure 39: EMR3 Definition ........................................................................................................................... 77
Figure 40: DDR2 Power-Up and Initialization ................................................................................................. 78
Figure 41: Example: Meeting
t
RRD (MIN) and
t
RCD (MIN) .............................................................................. 81
Figure 42: Multibank Activate Restriction ....................................................................................................... 82
Figure 43: READ Latency ............................................................................................................................... 84
Figure 44: Consecutive READ Bursts .............................................................................................................. 85
Figure 45: Nonconsecutive READ Bursts ........................................................................................................ 86
Figure 46: READ Interrupted by READ ............................................................................................................ 87
Figure 47: READ-to-WRITE ............................................................................................................................ 87
Figure 48: READ-to-PRECHARGE – BL = 4 ...................................................................................................... 88
Figure 49: READ-to-PRECHARGE – BL = 8 ...................................................................................................... 88
Figure 50: Bank Read – Without Auto Precharge .............................................................................................. 90
PDF: 09005aef85a711f4
1gb_ddr2_ait-aat_u88b.pdf – Rev. A 05/14 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.

MT47H128M8SH-25EAIT:M Related Products

MT47H128M8SH-25EAIT:M MT47H128M8SH-25EAAT:M MT47H64M16NF-25EAAT:M MT47H64M16NF-25EAIT:M
Description DDR DRAM, 128MX8, 0.4ns, CMOS, PBGA60, 8 X 10 MM, ROHS COMPLIANT, FBGA-60 DDR DRAM, 128MX8, 0.4ns, CMOS, PBGA60, 8 X 10 MM, ROHS COMPLIANT, FBGA-60 DDR DRAM, 64MX16, 0.4ns, CMOS, PBGA84, 8 X 12.50 MM, ROHS COMPLIANT, FBGA-84 DDR DRAM, 64MX16, 0.4ns, CMOS, PBGA84, 8 X 12.50 MM, ROHS COMPLIANT, FBGA-84
Is it Rohs certified? conform to conform to conform to conform to
Maker Micron Technology Micron Technology Micron Technology Micron Technology
package instruction TFBGA, TFBGA, TFBGA, TFBGA,
Reach Compliance Code compli compliant compliant compliant
access mode MULTI BANK PAGE BURST MULTI BANK PAGE BURST MULTI BANK PAGE BURST MULTI BANK PAGE BURST
Maximum access time 0.4 ns 0.4 ns 0.4 ns 0.4 ns
Other features AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH
JESD-30 code R-PBGA-B60 R-PBGA-B60 R-PBGA-B84 R-PBGA-B84
length 10 mm 10 mm 12.5 mm 12.5 mm
memory density 1073741824 bi 1073741824 bit 1073741824 bit 1073741824 bit
Memory IC Type DDR DRAM DDR DRAM DDR DRAM DDR DRAM
memory width 8 8 16 16
Number of functions 1 1 1 1
Number of ports 1 1 1 1
Number of terminals 60 60 84 84
word count 134217728 words 134217728 words 67108864 words 67108864 words
character code 128000000 128000000 64000000 64000000
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
organize 128MX8 128MX8 64MX16 64MX16
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TFBGA TFBGA TFBGA TFBGA
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
Filter level AEC-Q100 AEC-Q100 AEC-Q100 AEC-Q100
Maximum seat height 1.2 mm 1.2 mm 1.2 mm 1.2 mm
self refresh YES YES YES YES
Maximum supply voltage (Vsup) 1.9 V 1.9 V 1.9 V 1.9 V
Minimum supply voltage (Vsup) 1.7 V 1.7 V 1.7 V 1.7 V
Nominal supply voltage (Vsup) 1.8 V 1.8 V 1.8 V 1.8 V
surface mount YES YES YES YES
technology CMOS CMOS CMOS CMOS
Terminal form BALL BALL BALL BALL
Terminal pitch 0.8 mm 0.8 mm 0.8 mm 0.8 mm
Terminal location BOTTOM BOTTOM BOTTOM BOTTOM
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
width 8 mm 8 mm 8 mm 8 mm
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