IDT72V251L20J datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > storage> IDT72V251L20J

IDT72V251L20J: Description512 X 9 OTHER FIFO, 12 ns, PQCC32; Categorystorage; File Size117KB，14 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

Download Datasheet Parametric View All

IDT72V251L20J Overview

512 X 9 OTHER FIFO, 12 ns, PQCC32

IDT72V251L20J Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	32
Maximum operating temperature	70 Cel
Minimum operating temperature	0.0 Cel
Maximum supply/operating voltage	3.6 V
Minimum supply/operating voltage	3 V
Rated supply voltage	3.3 V
maximum access time	12 ns
Processing package description	PLASTIC, LCC-32
state	ACTIVE
Craftsmanship	CMOS
packaging shape	RECTANGULAR
Package Size	CHIP CARRIER
surface mount	Yes
Terminal form	J BEND
Terminal spacing	1.27 mm
terminal coating	TIN LEAD
Terminal location	QUAD
Packaging Materials	PLASTIC/EPOXY
Temperature level	COMMERCIAL
memory width	9
organize	512 X 9
storage density	4608 deg
operating mode	SYNCHRONOUS
Number of digits	512 words
Number of digits	512
cycle	20 ns
Output enable	Yes
Memory IC type	OTHER FIFO

Preview

Download Datasheet

View All

3.3 VOLT CMOS SyncFIFO™

256 x 9, 512 x 9,

1,024 x 9, 2,048 x 9,

4,096 x 9 and 8,192 x 9

IDT72V201, IDT72V211

IDT72V221, IDT72V231

IDT72V241, IDT72V251

FEATURES:

•

256 x 9-bit organization IDT72V201

512 x 9-bit organization IDT72V211

1,024 x 9-bit organization IDT72V221

2,048 x 9-bit organization IDT72V231

4,096 x 9-bit organization IDT72V241

8,192 x 9-bit organization IDT72V251

10 ns read/write cycle time

5V input tolerant

Read and Write clocks can be independent

Dual-Ported zero fall-through time architecture

Empty and Full Flags signal FIFO status

Programmable Almost-Empty and Almost-Full flags can be set to

any depth

Programmable Almost-Empty and Almost-Full flags default to

Empty+7, and Full-7, respectively

Output Enable puts output data bus in high-impedance state

Advanced submicron CMOS technology

Available in 32-pin plastic leaded chip carrier (PLCC) and 32-pin

plastic Thin Quad FlatPack (TQFP)

Industrial temperature range (–40°C to +85°C) is available

DESCRIPTION:

The IDT72V201/72V211/72V221/72V231/72V241/72V251 SyncFIFOs™

are very high-speed, low-power First-In, First-Out (FIFO) memories with

clocked read and write controls. The architecture, functional operation and pin

assignments are identical to those of the IDT72201/72211/72221/72231/

72241/72251, but operate at a power supply voltage (Vcc) between 3.0V and

3.6V. These devices have a 256, 512, 1,024, 2,048, 4,096 and 8,192 x 9-bit

memory array, respectively. These FIFOs are applicable for a wide variety of

data buffering needs such as graphics, local area networks and interprocessor

communication.

These FIFOs have 9-bit input and output ports. The input port is

controlled by a free-running clock (WCLK), and two Write Enable pins

(WEN1, WEN2). Data is written into the Synchronous FIFO on every rising

clock edge when the Write Enable pins are asserted. The output port is

controlled by another clock pin (RCLK) and two Read Enable pins (REN1,

REN2).

The Read Clock can be tied to the Write Clock for single clock

operation or the two clocks can run asynchronous of one another for dual-

clock operation. An Output Enable pin (OE) is provided on the read port

for three-state control of the output.

The Synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF).

Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are

provided for improved system control. The programmable flags default to

Empty+7 and Full-7 for

PAE

and

PAF,

respectively. The programmable flag

offset loading is controlled by a simple state machine and is initiated by asserting

the Load pin (LD).

These FIFOs are fabricated using IDT's high-speed submicron CMOS

technology.

FUNCTIONAL BLOCK DIAGRAM

WCLK

WEN1

WEN2

INPUT REGISTER

OFFSET REGISTER

PAE

PAF

- D

WRITE CONTROL

LOGIC

RAM ARRAY

256 x 9, 512 x 9,

1,024 x 9, 2,048 x 9,

4,096 x 9, 8,192 x 9

FLAG

LOGIC

WRITE POINTER

READ POINTER

READ CONTROL

LOGIC

OUTPUT REGISTER

RESET LOGIC

RCLK

REN1

REN2

- Q

4092 drw 01

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

FEBRUARY 2002

DSC-4092/2

Recommended Resources

Half-wave capacitor step-down rectifier circuit a

Lighting delay circuit using single-junction transistor Part 2a

RTS706C circuit

Simple window detector circuit diagram

Electronic ballast circuit using TDA4918 to drive halogen lamp

34 Most Important Questions You Should Know When Doing DSP Development: 34 most important questions to know when developing DSP 1. What is DSP? (Default) 2. What are the main differences between DSP C language and host C language? 1) DSP C language is standard ANSI C, whi...; 37°男人 DSP and ARM Processors

C language clock program prompts error in KEIL: #include#define uchar unsigned char #define uint unsigned int char DATA_7SEG[10]={0xC0,0xF9,0xA4,0xB0,0x99, 0x92,0x82,0xF8,0x80,0x90,};/*0~9 digital tube segment code*/ uchar hour=0,min=0,sec=0; /*Hou...; youshx MCU

Basic Concepts of Circuits: Current The directional movement of electric charge is called current. Current is usually represented by I in a circuit. There are two types of current: direct current and alternating current. The mag...; zdr MCU

How to calculate the current after the voltage is stepped down by the Zener diode?: As shown in the figure, how much current can a 10-ohm resistor theoretically provide?...; vincent.liu Analog electronics

EMC Compliant Single-Chip Resolver-to-Digital Converter (RDC) Reference Design: [i=s]This post was last edited by qwqwqw2088 on 2020-6-28 07:50[/i]The design provides a solution for EMC-compliant resolver-to-digital converters (RDCs) with a single-chip PGA411-Q1 with 12-bit angul...; qwqwqw2088 Analogue and Mixed Signal

TI C6000 Data Storage Processing and Performance Optimization: Memory is to CPU like warehouse is to workshop. Raw materials, semi-finished products, finished products, etc. in the workshop processing process need to be in and out of the warehouse. No matter how ...; Jacktang DSP and ARM Processors

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components