W3EG7262S202JD3 datasheet, PDF

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W3EG7262S202JD3: DescriptionDDR DRAM Module, 64MX8, 0.75ns, CMOS, ROHS COMPLIANT, DIMM-184; Categorystorage storage; File Size280KB，12 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com; Environmental Compliance

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W3EG7262S202JD3 Overview

DDR DRAM Module, 64MX8, 0.75ns, CMOS, ROHS COMPLIANT, DIMM-184

W3EG7262S202JD3 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	conform to
Objectid	1820294802
Parts packaging code	DIMM
package instruction	DIMM,
Contacts	184
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	DUAL BANK PAGE BURST
Maximum access time	0.75 ns
Other features	AUTO/SELF REFRESH; LG-MAX; WD-MAX
JESD-30 code	R-XDMA-N240
length	133.48 mm
memory density	536870912 bit
Memory IC Type	DDR DRAM MODULE
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	184
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64MX8
Package body material	UNSPECIFIED
encapsulated code	DIMM
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	30.48 mm
self refresh	YES
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.81 mm

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White Electronic Designs

W3EG7262S-D3

-JD3

PRELIMINARY*

512MB – 2X32Mx72 DDR SDRAM UNBUFFERED

FEATURES

Double-data-rate architecture

DDR200 and DDR266

• JEDEC design speciﬁed

Bi-directional data strobes (DQS)

Differential clock inputs (CK & CK#)

Programmable Read Latency 2,2.5 (clock)

Programmable Burst Length (2,4,8)

Programmable Burst type (sequential & interleave)

Edge aligned data output, center aligned data input.

Auto and self refresh

Serial presence detect

Dual Rank

Power supply: 2.5V ± 0.2V

JEDEC184 pin DIMM package

• JD3 PCB height: 30.48mm (1.20")

NOTE: Consult factory for availability of:

• RoHS compliant products

• Vendor source control options

• Industrial temperature option

* This product is under development, is not qualiﬁed or characterized and is subject to

change without notice.

DESCRIPTION

The W3EG7262S is a 2x32Mx72 Double Data Rate

SDRAM memory module based on 256Mb DDR SDRAM

components. The module consists of eighteen 32Mx8

DDR SDRAMs in 66 pin TSOP packages mounted on a

184 pin FR4 substrate.

Synchronous design allows precise cycle control with the

use of system clock. Data I/O transactions are possible on

both edges and Burst Lengths allow the same device to be

useful for a variety of high bandwidth, high performance

memory system applications.

OPERATING FREQUENCIES

DDR266 @CL=2

Clock Speed

CL-t

RCD

-t

133MHz

2-2-2

DDR266 @CL=2.5

133MHz

2.5-3-3

DDR200 @CL=2

100MHz

2-2-2

May 2005

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

W3EG7262S202JD3 Related Products

	W3EG7262S202JD3	W3EG7262S265D3	W3EG7262S202D3	W3EG7262S262D3	W3EG7262S262JD3
Description	DDR DRAM Module, 64MX8, 0.75ns, CMOS, ROHS COMPLIANT, DIMM-184	DDR DRAM Module, 64MX8, 0.75ns, CMOS, ROHS COMPLIANT, DIMM-184	DDR DRAM Module, 64MX8, 0.75ns, CMOS, ROHS COMPLIANT, DIMM-184	DDR DRAM Module, 64MX8, 0.75ns, CMOS, ROHS COMPLIANT, DIMM-184	DDR DRAM Module, 64MX8, 0.75ns, CMOS, ROHS COMPLIANT, DIMM-184
Parts packaging code	DIMM	DIMM	DIMM	DIMM	DIMM
package instruction	DIMM,	DIMM,	DIMM,	DIMM,	DIMM,
Contacts	184	184	184	184	184
Reach Compliance Code	unknown	unknown	unknown	unknown	unknow
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST
Maximum access time	0.75 ns	0.75 ns	0.75 ns	0.75 ns	0.75 ns
Other features	AUTO/SELF REFRESH; LG-MAX; WD-MAX	AUTO/SELF REFRESH; LG-MAX; WD-MAX	AUTO/SELF REFRESH; LG-MAX; WD-MAX	AUTO/SELF REFRESH; LG-MAX; WD-MAX	AUTO/SELF REFRESH; LG-MAX; WD-MAX
JESD-30 code	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240
length	133.48 mm	133.48 mm	133.48 mm	133.48 mm	133.48 mm
memory density	536870912 bit	536870912 bit	536870912 bit	536870912 bit	536870912 bi
Memory IC Type	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE
memory width	8	8	8	8	8
Number of functions	1	1	1	1	1
Number of ports	1	1	1	1	1
Number of terminals	184	184	184	184	184
word count	67108864 words	67108864 words	67108864 words	67108864 words	67108864 words
character code	64000000	64000000	64000000	64000000	64000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C
organize	64MX8	64MX8	64MX8	64MX8	64MX8
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	DIMM	DIMM	DIMM	DIMM	DIMM
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	30.48 mm	30.48 mm	30.48 mm	30.48 mm	30.48 mm
self refresh	YES	YES	YES	YES	YES
Maximum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
Minimum supply voltage (Vsup)	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	NO	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL
width	3.81 mm	3.81 mm	3.81 mm	3.81 mm	3.81 mm
Objectid	1820294802	1820294817	1820294797	-	-

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