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WED3EG72M18S335JD3ISG

Description
DDR DRAM Module, 16MX72, 0.7ns, CMOS, ROHS COMPLIANT, DIMM-184
Categorystorage    storage   
File Size246KB,12 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Environmental Compliance  
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WED3EG72M18S335JD3ISG Overview

DDR DRAM Module, 16MX72, 0.7ns, CMOS, ROHS COMPLIANT, DIMM-184

WED3EG72M18S335JD3ISG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerMicrosemi
Parts packaging codeDIMM
package instructionDIMM,
Contacts184
Reach Compliance Codecompli
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time0.7 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-XDMA-N184
JESD-609 codee4
memory density1207959552 bi
Memory IC TypeDDR DRAM MODULE
memory width72
Number of functions1
Number of ports1
Number of terminals184
word count16777216 words
character code16000000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize16MX72
Package body materialUNSPECIFIED
encapsulated codeDIMM
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
self refreshYES
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)2.5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceGold (Au)
Terminal formNO LEAD
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
White Electronic Designs
WED3EG7218S-JD3
PRELIMINARY*
128MB – 16Mx72 DDR SDRAM UNBUFFERED
FEATURES
Double-data-rate architecture
DDR200, DDR266, DDR333 and DDR400
• JEDEC design specified
BI-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Power supply:
V
CC
= V
CCQ
= 2.5V±0.2V
(100, 133 and 166MHz)
V
CC
= V
CCQ
= 2.6V±0.1V
(200MHz)
* This product is under development, is not qualified or characterized and is subject to
change without notice.
DESCRIPTION
The WED3EG7218S is a 16Mx72 Double Data Rate
SDRAM memory module based on 128Mb DDR SDRAM
component. The module consists of nine 16Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
JEDEC 184 pin DIMM package
• JD3 PCB height: 30.48 (1.20") Max
NOTE: Consult factory for availability of:
• RoHS Products
• Vendor source control options
• Industrial temperature option
OPERATING FREQUENCIES
DDR400 @CL=3
Clock Speed
CL-t
RCD
-t
RP
200MHz
3-3-3
DDR333 @CL=2.5
166MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
June 2006
Rev. 2
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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